Riet Labie

Cu/Sn microbumps interconnect for 3D TSV chip stacking

The electronics industry is increasingly looking to 3D integration in order to address the ever continuing product needs of miniaturization and performance increase for future generation of ICs. Most of these integration schemes require multiple die stacking on top of each other. In this work, transient liquid phase (TLP) bonding technique using Cu-Sn intermetallic is used for die stacking. Fast die to wafer pick and place operation followed by collective bonding process is described here for bonding application. Low temperature stacking is also explored using solid metal bonding (SMB) process and the effect of various cleaning agents on the bonding interface is discussed. Finally, in this paper we report on die stacking using microbumps with dies containing through silicon visa (TSV).

Reliability testing of Cu-Sn intermetallic micro-bump interconnections for 3D-device stacking

In this work, two different reliability experiments, thermal cycling and electromigration, are performed on fully packaged Si-to-Si stacks bonded with Cu-Sn intermetallic (IMC) micro-bumps. These experiments investigate both the more critical thermo-mechanical behavior as well as the expected positive thermal-electrical behavior. The Cu-Sn IMC bumps survive thermal cycling for more than 3900 cycles between −40 and 125°C with 1 hour per cycle. The resistance to electromigration is strongly dependant on the used Sn thickness and shows an improved performance for thinner Sn samples (3.5µm) compared to thicker Sn (8µm). In either case, IMC bumps outperform standard solder flip chip bumps.

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for a High-k/Metal Gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area.

Influence of the processing method on the amount and development of voids in miniaturized interconnections

For satisfying the current industrial need of downscaling electronic devices, the die-to-die or die-to-package interconnects need to decrease in size accordingly. In view of that, flip chip bumps, which are currently the smallest interconnect type, have to be further miniaturized. In this study, Cu-Sn-Cu TLP (Transient Liquid Phase) bonded bumps that consist entirely of intermetallics (IMC) are studied. The overall intermetallic properties are not yet well understood. Microstructural inspection of these bumps revealed the presence of voids inside the IMC phase and since the mechanical behavior of the bumps is strongly affected by it, a first study is executed to better understand the cause of voiding. It is shown that the appearance of voids is directly related to processing and especially to the use of cleaning agents. Therefore a study of the three different types of bumps microstructures produced by the use of three types of cleaning agents has been conducted. For understanding the influence of the processing method on the amount and development of voids during ageing, in addition to a study of bumps, Cu-Sn-Cu blanket film sandwich structures have been investigated as well. Addition of an extra layer of Ni into the Cu-Sn-Cu system was performed in order to observe its influence on voiding occurrence.

Investigation of Co UBM for direct bumping on Cu/LowK dies

When changing to lead-free solders, also the under hump metallurgy (UBM) needs to be re-investigated and possibly redefined. In this paper, CO is investigated on its applicability as under bump metal for CUnow K dies. The interaction of CO in combination with SnPb and pure Sn humps is studied. Since during annealing a meta-stable Sn - Co(Cu) phase forms, CO cannot act as diffusion barrier for Cu. Nevertheless, the use of CO as UBM with Sn-solder is successful. No signs of degradation of Cu-Co-Sn bumps are noticed till 15M)h at 150