Chukwudi Okoro

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single- and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

Cu pumping in TSVs: Effect of pre-CMP thermal budget

Abstract When Cu ‘Through-Silicon-Vias’ (TSVs) are exposed to high temperatures as typically encountered during the back-end of line (BEOL) processing, the higher coefficient of thermal expansion (CTE) of Cu forces it to expand more than Si. This causes compressive stress in the confined Cu inside the TSV. This stress can partly be released near the top of the TSV, by out-of-plane expansion of the Cu, the so-called ‘Cu pumping’. It can severely damage the BEOL layers. In this paper the effect of a pre-CMP thermal budget (temperature and time) on Cu pumping is studied for various Cu chemistries and TSV aspect ratios. It is shown that to suppress Cu pumping a pre-CMP anneal is required that is either very long or at a temperature very close to the maximum temperature used in the BEOL processing.

Influence of annealing conditions on the mechanical and microstructural behavior of electroplated Cu-TSV

In this paper, the effect of annealing condition on the microstructural and mechanical behavior of copper through-silicon via (Cu-TSV) is studied. The hardness of Cu-TSV scaled with the Hall–Petch relation, with the average hardness values of 1.9 GPa, 2.2 GPa and 2.3–2.8 GPa, respectively for the annealed, room temperature (RT) aged and the as-deposited samples. The increase in hardness toward the top of the as-deposited sample is related to the decrease in grain size. The annealed and the as-deposited samples showed a constant elastic modulus (E-modulus) value across the length of Cu-TSV of 140 GPa and 125 GPa respectively, while the RT aged sample showed a degradation in E-modulus from the bottom of the TSV (140 GPa) to the top (110 GPa). These differences in E-modulus values and trends under the different test conditions were found to be unrelated with the crystallographic texture of the samples, but could be related to the presence of residual stresses. No correlation is found between the hardness and E-modulus data. This is attributed to the coupling and competitive effects of grain size and residual stresses, with the grain size effect having a dominant influence on hardness, while the presence of residual stresses dominated the E-modulus result.

Analysis of the Induced Stresses in Silicon During Thermcompression Cu-Cu Bonding of Cu-Through-Vias in 3D-SIC Architecture

A new approach to 3D stacking of chips is being developed at IMEC and is called 3D-stacked IC (3D-SIC). In this approach, interconnection between strata is achieved by thermo-compression bonding of Cu-vias to a Cu-landing pad. In this paper we use finite element methods to study the influence of the resultant induced stresses in silicon as a result of CTE mismatch between silicon and copper and that also caused by the applied thermo-compression bonding force. Bonding temperature is found to be the main cause of induced stresses during thermo-compression bonding. The induced stresses decreased with a decrease in the silicon thickness. The keep-away-zone of the transistors from the influence of stresses from the Cu-vias is found to be dependent on the diameter of the Cu-via and the doping concentration of the transistors.

Thermo-mechanics of 3D-wafer level and 3D stacked IC packaging technologies

The miniaturisation 3D integration/stacking systems has a significant impact on both thermal resistance and thermo-mechanical reliability. The trends regarding these issues are summarised for the different 3D integration approaches: 3D-SIP, 3D-WLP and 3D-SIC.

Polymer Filling of Silicon Trenches for 3-D Through Silicon vias Applications

Ring-shaped silicon trenches with a depth of 50 were filled with different spin-on dielectric (SOD) polymers. Ultimately, the polymer should serve as deep trench isolation layers, also called liners, for 3-D wafer-level packaging through silicon vias (TSVs). TSVs allow the vertical stacking and interconnection of multiple devices. 3-D packaging is an emerging technology that can be an alternative solution to scaling issues in complementary metal oxide semiconductors. SODs with different electrical, chemical, and mechanical properties were tested. The filling was conducted using spin coating, which is a readily available technology. In order to improve the filling performances, a prewetting solvent was applied prior to coating. Contact angle measurements were carried out to assess the polymer wetting properties. Without prewetting, it was observed that too high an affinity for the wafer surface was probably detrimental. With prewetting, the wetting was improved but this did not significantly modify the filling itself. The filling was rather improved due to the mechanical action of the solvent. Overall, most of the SOD could successfully fill the trenches, however, stress-related delamination could almost always be detected at the polymer/silicon interface. A stress study was carried out by finite element modeling in order to address the delamination issue. It was concluded that the level of stress is mainly governed by the cure temperature and other mechanical properties. This paper concludes with some recommendations on the choice of an SOD for filling applications.

Elimination of the axial deformation problem of Cu-TSV in 3D integration

The out‐of‐plane expansion of Copper Through‐Silicon‐Via (Cu‐TSV) is a concern in 3D stacking of chips, since it pushes against the BEOL, thus posing a possible reliability risk. In this study we demonstrate a solution for the Cu‐TSV out‐of‐plane expansion problem resulting in a non‐deformed BEOL. This is achieved through gaining a good understanding of the thermo‐mechanical behavior of Cu by experiments and adopting this learning in our process flow.

Prediction of the Influence of Induced Stresses in Silicon on CMOS Performance in a Cu-Through-Via Interconnect Technology

One approach to 3D chip stacking and integration is to process filled Cu-vias into the Si and to attach them to a next level die by means of thermocompression bonding. This results in induced stresses in the silicon due to the large CTE disparity between copper and silicon, and also from the force applied during thermocompression bonding. These stresses can have an impact on the performance of the transistors and may as well result in die fracture. This paper studies these stresses through Finite Element modeling. We found that the keep-away- zone of the transistors from the copper via where transistor performance is impacted by the through-Si interconnect proximity, is proportional to the via diameter. The bonding temperature is found to be the main cause for the induced stresses during the thermocompression bonding process. The induced stresses in silicon decrease with decreasing the silicon thickness.

Impact of thinning and through silicon via proximity on High-k / Metal Gate first CMOS performance

3D integration has the potential to alleviate the performance limitations that CMOS scaling is facing provided that it preserves the integrity of both front end and back end devices and constituting materials. The impact of wafer thinning and of the proximity of through silicon via on active devices, back end structures, ring oscillators and mixed signal circuit are reported for the first time for a High-k/Metal Gate first strained CMOS technology with low-k BEOL. The relative stress induced by the STI and the TSV are measured by micro-Raman spectroscopy. The measured impact of the stress on a sensitive DAC circuit is used to define a safe keep out area.

Insertion bonding: A novel Cu-Cu bonding approach for 3D integration

A novel low temperature Cu-Cu bonding approach called the insertion bonding technique has been developed. This technique leverages on the initiation of high shear stresses at metal-metal contact interface, thus resulting in high plastic deformation, which is essential for strong bond formation. Through finite element studies, it is observed that the insertion bonding technique result in significantly larger plastic deformation in comparison to the conventional bonding technique under the same bonding conditions. Experimental studies of the insertion bonding technique were performed and it is observed that a seamless bond interface is achieved, even at a low bonding temperature of 100°C. Bonding at room temperature (RT) in the presence of a surface cleaning agent resulted in an improved bond interface. Resistance measurement of the samples bonded at 100°C revealed that an electrical contact is achieved between the stacked dies. This shows that the insertion bonding techniques holds much promise for low temperature Cu-Cu bonding.