Paresh Limaye

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.

Thermal cycling reliability of SnAgCu and SnPb solder joints : A comparison for several IC-packages

This paper deals with a comparison study between SnPb and SnAgCu solder joint reliability. The comparison is based on non-linear finite element modellin. Three packages have been selected: silicon CSP, underfilled flip chip and QFN package. Also the effect of thermal cycling conditions has been investigated. Comparing the induced inelastic strains in the solder joint, the leadfree SnAgCu generally scores better thanks to the lower creep strain rate. On the other hand for the CSP and flip chip package, SnAgCu scores worse for the more extreme loading conditions when the inelastic dissipated energy density is selected as damage parameter. The main reason is that due to the lower creep strain rate, the stresses become higher for SnAgCu resulting in higher hysteresis loops with more dissipated energy per cycle. For the QFN package, SnAgCu scores much better.

High density Cu-Sn TLP bonding for 3D integration

3D die stacking is a key technology for enabling 3D integration wherein two or more dies are stacked on top of each other with vertical interconnections. This result in high speed interconnects with reduced noise and crosstalk as compared to wire bonded assemblies. 3D integration may require sequential stacking of multiple dies without disturbing the previously bonded die. This can be achieved by transient liquid phase (TLP) bonding where the melting point of the intermetallic formed after the bonding is much higher than that of the solder itself. In this paper, we demonstrate the feasibility of narrow pitch TLP bonding for the Cu-Sn system in die stacking applications. Furthermore, we explore several process options for cost reduction, throughput enhancement and thermal budget minimization. More than 90% yielding devices are achieved on 40µm pitch peripheral array and 100µm pitch area array dies at 250°C using both flux and No flow UnderFill (NUF) using both die-to-die and die-to-wafer setup. Preliminary bonding results at temperature less than 200°C are also presented.

Influence of Intermetallic Properties on Reliability of Lead-Free Flip-Chip Solder Joints

Electroplated pure tin bumping as a lead-free alternative for ultra fine pitch applications is a relatively easy process and has provided us with comparable results to eutectic Sn/Pb for thermal cycling reliability. Experimentally, it has been reported that a significantly higher (~40%) thermal cycle fatigue life is seen with the use of cobalt under bump metallization (UBM) instead of copper UBM for a flip-chip device assembled on an alumina substrate. In the current approaches used to estimate fatigue life of solder joints, the solder joint is treated as a homogenous material and modeled as such. However, the smaller joint sizes and higher reactivity of Sn implies that a larger amount of intermetallics are formed as a percentage of bump volume. The existing approach cannot account for the influence on the fatigue behavior of these intermetallic layers within the solder joint. In order to investigate if a simplified engineering approach can provide some insight into this issue, we have attempted to explicitly model the intermetallics as a continuous but separate part of the solder joint. The main damage parameter investigated is the accumulated inelastic strain in a single thermal cycle. From the results, it is clear that the Youngs modulus of the intermetallic layer plays an important role, more so when the ratio of intermetallic thickness to the solder joint standoff increases. Thickness of the intermetallic layer also influences the overall strain accumulation in the same manner. The CTE of the intermetallic layer has a relatively lesser influence on the strain accumulation. Both the experimental and FE results suggest that changing the UBM from copper to cobalt can improve the fatigue life by 20%-30%.

Fine pitch Cu/Sn solid state diffusion bonding for making high yield bump interconnections and its application in 3D integration

Low temperature stacking of dies for 3D integration has been gaining interest due to the thermal sensitivity of some advanced node devices such as DRAM. Sn-based solder joint is considered as a promising approach for making die to die interconnections because Sn to Cu bonding temperature is lower and the yield is higher as compared with Cu to Cu bonding. This paper presents a systematic study of Cu/Sn solid state diffusion bonding, during which the CuSn intermetallic compounds are formed by the solid state inter-diffusion. It is found that there is a lower-limit pressure of about 20 MPa below that there is no sufficient Sn plastic deformation to ensure good contact and electrical connection. However, 150 MPa is almost the upper-limit beyond which Sn will squeeze out much leading to electrical short between adjacent bumps. Surface cleaning or oxides removal is found to be another key factor for good bonding. Finally, this Cu/Sn solid state diffusion bonding together with Cu TSV are implemented into the 3D integration flow for making die to die vertical interconnection.

Analytical and finite element models of the thermal behavior for lead-free soldering processes in electronic assembly

The development of a simplified analytical model to describe the thermal history of a printed circuit board assembly (PCA) during convective reflow soldering is described in this paper. Verification of the assumptions was done by finite element modeling, as well as comparison with experimental measured temperature profiles.

Thermal Cycle Reliability of 3D Chip Stacked Package Using Pb-free Solder Bumps: Parameter Study by FEM Analysis

This study is aimed at analysing the reliability of a three-dimensional (3D) chip stacked package under cyclic thermal loading. The critical areas in the 3D chip stacked package are defined with finite element modeling (FEM) based simulations to correlate the thermal cycling experiments. The 3D chip stacked package consists of two 300mum thick Si chips vertically connected with Sn-Ag-Cu solder bump joints and then assembled on a conventional FR-4 printed circuit aboard (PCB). Two thermal cycle conditions are studied, namely: -40 to 125degC and 0 to 100degC. FEM simulations indicate that in both conditions, the critical failure location is expected to be in the chip side region of the corner solder bump of the lower chip connecting the package to the PCB. Creep strain per single thermal cycle averaged over a critical damage volume; Deltaepsivcr is used as the damage parameter. Furthermore, we have investigated the possible approaches to improve the thermo-mechanical reliability for this package. The results indicate that adding an underfill or thinning Si chips will achieve lower creep strain in solder bumps. Furthermore, the stress levels in Si and Cu via in the Si chip are low. Therefore fracture of Si chips and fatigue of Cu vias is not expected under thermal cycling conditions

Insertion bonding: A novel Cu-Cu bonding approach for 3D integration

A novel low temperature Cu-Cu bonding approach called the insertion bonding technique has been developed. This technique leverages on the initiation of high shear stresses at metal-metal contact interface, thus resulting in high plastic deformation, which is essential for strong bond formation. Through finite element studies, it is observed that the insertion bonding technique result in significantly larger plastic deformation in comparison to the conventional bonding technique under the same bonding conditions. Experimental studies of the insertion bonding technique were performed and it is observed that a seamless bond interface is achieved, even at a low bonding temperature of 100°C. Bonding at room temperature (RT) in the presence of a surface cleaning agent resulted in an improved bond interface. Resistance measurement of the samples bonded at 100°C revealed that an electrical contact is achieved between the stacked dies. This shows that the insertion bonding techniques holds much promise for low temperature Cu-Cu bonding.

Surface planarization of Cu/Sn micro-bump and its application in fine pitch Cu/Sn solid state diffusion bonding

Low temperature stacking of dies for 3D integration has been gaining interest due to the thermal sensitivity of some advanced node devices such as DRAM. Sn-based solder joint is considered as a promising approach for making die to die interconnections due to its low bonding temperature and high yield. Previously the Cu/Sn solid state diffusion bonding at 150 °C was reported, during which the bonding pressure is typically of 50 MPa. The remaining challenge for fine pitch Cu/Sn solid state diffusion bonding is how to enable good bonding for micro-bump with high topography. The effect of improving the contact between bumps was studied by applying a fly-cutting process to trim Cu/Sn bump surface. First, 2 kinds of fly-cutting processes, named fly-cutting first and seed etch first, are studied. Then different combinations such as fly-cutted Cu to non-fly-cutted Sn and fly-cutted Cu to fly-cutted Sn are compared. It is found that Cu and Sn micro-bumps with high topography become quite flat and smooth after fly-cutting, which ensure a smooth bonding interface. Moreover, ∼80% yielding devices are achieved on 40/15 µm pitch/spacing peripheral array dies at 150°C with NUF serving as an intermediate cleaning agent as well as permanent underfill. In general, fly-cutting is an attractive option in enabling a good solid state diffusion bonding for micro-bump with high surface non-uniformity.

Creep Behavior of Mixed SAC 405/SnPb Soldered Assemblies in Shear Loading

In this work, the creep behavior of mixed lead free (Sn4%Ag 0.5%Cu) (SAC 405) and eutectic tin lead (Sn37%Pb) solders has been studied. A double lap shear configuration was used to study the creep response of the mixed solder joints, the dimensions of which ranged from 300 to 500 mum. The tested solder specimens were wafer level chip scale packages (WLCSP) bumped with preformed solder spheres. The volume ratios of the two solders were controlled by using preformed solders spheres in the size range of 300 to 450 mum. All the specimens were reflowed at a profile with 260degC peak temperature resulting in a complete mixing of the two solder alloys. The creep tests were done at constant stress levels by applying a constant load to the specimen. The displacement of the joints was recorded as a function of time from which the steady state strain rates were determined. In the present experiments, these ranged from lE-3/s to lE-9/s. while the applied stress levels ranged from 5 MPa to 40 MPa. The tests were repeated for 3 different temperatures: 40degC, 70degC and 100degC. The stress - strain rate data seems to fit well to the SINH creep model and the obstacle controlled model. The fitting to the power law shows different slopes above and below 10 MPa stress levels. In addition, the effect of isothermal aging at 125degC on the creep behavior was also studied. In general, the mixed solder joints creep faster than SAC 405 and their deformation rate lies in between that of the eutectic SnPb and SAC 405 solders.