Robert W. Martell

Circuit and method for scheduling instructions by predicting future availability of resources required for execution

Trace event detection during trace enable transitions

Non-clocked early read for back-to-back scheduling of instructions

Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution

Apparatus for pipeline streamlining where resources are immediate or certainly retired

Method and apparatus for performing multiple load operations to the same memory location in a computer system

Method and apparatus for recovering the state of a speculatively scheduled operation in a processor which cannot be executed at the speculated time

Method and apparatus for scheduling the dispatch of instructions from a reservation station

Method and apparatus for pipeline streamlining where resources are immediate or certainly retired

Method and apparatus for avoiding writeback conflicts between execution units sharing a common writeback path