Noah Zamdmer

Frequency-independent equivalent-circuit model for on-chip spiral inductors

A wide-band physical and scalable 2-/spl Pi/ equivalent circuit model for on-chip spiral inductors is developed. Based on physical derivation and circuit theory, closed-form formulas are generated to calculate the RLC circuit elements directly from the inductor layout. The 2-/spl Pi/ model accurately captures R(f) and L(f) characteristics beyond the self-resonant frequency. Using frequency-independent RLC elements, this new model is fully compatible with both ac and transient analysis. Verification with measurement data from a SiGe process demonstrates accurate performance prediction and excellent scalability for a wide range of inductor configurations.

Record RF performance of 45-nm SOI CMOS Technology

We report record RF performance in 45-nm silicon-on- insulator (SOI) CMOS technology. RF performance scaling with channel length and layout optimization is demonstrated. Peak fTs of 485 GHz and 345 GHz are measured in floating- body NFET and PFET with nearby wiring parasitics (i.e., gate- to-contact capacitance) included after de-embedding, thus representing FET performance in a real design. The measured fTs are the highest ever reported in a CMOS technology. Body- contacted FETs are also analyzed that have layout optimized for high-frequency analog applications. Employing a notched body contact layout, we reduce parasitic capacitance and gate leakage current significantly, thus improving RF performance with low power. For longer than minimum channel length and a body-contacted NFET with notched layout, we measure a peak fT of 245 GHz with no degradation in critical analog figures of merit, such as self-gain.

Frequency-independent equivalent circuit model for on-chip spiral inductors

A wide-band, physical and scalable 2-/spl Pi/ equivalent circuit model for on-chip spiral inductors is developed. Using frequency-independent RLC elements, it accurately captures R(f) and L(f) characteristics beyond the self-resonant frequency. This new model is fully compatible with both AC and transient analysis. Verification with measurement data demonstrates excellent scalability for a wide range of inductor configurations.

RTA-Driven Intra-Die Variations in Stage Delay, and Parametric Sensitivities for 65nm Technology

We report, for the first time, a detailed study of intra-die variation (IDV) of CMOS inverter delay for the 65nm technology, driven by mm-scale variations of rapid thermal annealing (RTA). We find that variation in VT and REXT accounts for most of the IDV in delay and leakage and is modulated by lamp RTA ramp rate. We show a good correlation of inverter delay to mm-scale variation in the predicted reflectivity of the device pattern densities

Modeling of Variation in Submicrometer CMOS ULSI Technologies

The scaling of semiconductor technologies from 90- to 45-nm nodes highlights the need for accurate and predictive compact models that address the regime where small-scale physical effects become dominant. These demanding requirements on compact models extend beyond the core model to a suite of design tools that include extraction tools and statistical methods to account for unpredictable variation (e.g., random dopant fluctuations and polysilicon linewidth variation) and predictable variation (e.g., transistor response differences that are layout dependent). Layout-dependent or local environment differences are driven by factors such as lithography and novel performance-enhancing process techniques such as dual-stress nitride liner films. Sources of variation such as rapid thermal annealing temperature, low-frequency noise, and modeling of back-end-of-line elements need to be considered. The modeling of intradie and interdie variations, updated for small geometries, should be properly positioned in the design flow. This paper presents the challenges and results of compact modeling at the 65-nm node and beyond

A low-voltage 40-GHz complementary VCO with 15% frequency tuning range in SOI CMOS technology

The design of a low-voltage 40-GHz complementary voltage-controlled oscillator (VCO) with 15% frequency tuning range fabricated in 0.13-/spl mu/m partially depleted silicon-on-insulator (SOI) CMOS technology is reported. Technological advantages of SOI over bulk CMOS are demonstrated, and the accumulation MOS (AMOS) varactor limitations on frequency tuning range are addressed. At 1.5-V supply, the VCO core and each output buffer consumes 11.25 mW and 3 mW of power, respectively. The measured phase noise at 40-GHz is -109.73 dBc/Hz at 4-MHz offset from the carrier, and the output power is -8 dBm. VCO performance using high resistivity substrate (/spl sim/300-/spl Omega//spl middot/cm) has the same frequency tuning range but 2 dB better phase noise compared with using low resistivity substrate (10 /spl Omega//spl middot/cm). The VCO occupies a chip area of only 100 /spl mu/m by 100 /spl mu/m (excluding pads).

A 44GHz differentially tuned VCO with 4GHz tuning range in 0.12 /spl mu/m SOI CMOS

A differentially tuned VCO is fully integrated in a standard microprocessor 0.12 /spl mu/m SOI CMOS. A phase noise of -101.8dBc/Hz at 1MHz offset is measured with 7.5mW at 1.5V. The VCO tuning range is 9.8% from 40GHz to 44GHz. The output power is up to -6dBm after a single-stage buffer amplifier with 6mW at 1.5V.

A 243-GHz F/sub t/ and 208-GHz F/sub max/, 90-nm SOI CMOS SoC technology with low-power millimeter-wave digital and RF circuit capability

SOI CMOS technology offers low parasitic junction capacitance, and therefore provides speed and power enhancements to digital applications compared to bulk CMOS. It is also emerging as a good candidate for high-performance SoC, with integratable RF circuits that operate beyond 30-GHz already demonstrated at the 130-nm technology node. The digital aspects of the base 90-nm SOI technology were previously reported. This paper presents the RF performance of this technology, and shows that the capabilities of CMOS technology are expanding into the millimeter-wave regime.

A power-efficient 33 GHz 2:1 static frequency divider in 0.12-/spl mu/m SOI CMOS

A 2:1 static frequency divider was fabricated in a 0.12-/spl mu/m SOI CMOS technology. The divider exhibits a maximum operating frequency of 33 GHz. When the power consumption is scaled down to 2.7 mW, a maximum operating frequency of 25 GHz is measured.

High-performance three-dimensional on-chip inductors in SOI CMOS technology for monolithic RF circuit applications

This paper presents high-Q and high-inductance-density on-chip inductors fabricated on high-resistivity substrate (HRS) using a 0.12 /spl mu/m SOI CMOS technology with 8 copper metal layers. A peak Q of 52 is obtained at 5 GHz for a 0.6 nH STP (Single-turn, multiple metal levels in Parallel) inductor. An inductance density of 5302 fH//spl mu/m/sup 2/ is obtained for a 42 nH MTS (Multi-turn, multiple metal layers in Series) inductor.This paper presents high-Q and high-inductance-density on-chip inductors fabricated on high-resistivity substrate (HRS) using a 0.12 /spl mu/m SOI CMOS technology with 8 copper metal layers. A peak Q of 52 is obtained at 5 GHz for a 0.6 nH STP (Single-Turn, multiple metal levels in Parallel) inductor. An inductance density of 5302 fH//spl mu/m/sup 2/ is obtained for a 42 nH MTS (Multi-Turn, multiple metal layers in Series) inductor.