Roberto Gonella

Key reliability issues for copper integration in damascene architecture

Electromigration and the effects of Cu concentration in intra-metal dielectrics have been examined: these two key reliability issues are fundamental in the development of Cu based interconnects. Several experiments have been performed to highlight the sensitivity of the electromigration performances with respect to the various process variants: the impact of annealing, of dielectric capping SiN deposition process and the role of the environment on the diffusion mechanisms have been studied. Furthermore, the dependence of the line-width on the current and temperature induced transport mechanisms have been analyzed. Once more, process variations have been demonstrated to influence strongly the final behavior of Cu interconnects in dual-damascene architecture. Intra-metal dielectric reliability has also to be considered as a potential reliability issue and bias-temperature stress tests have proven that if the amount of Cu left behind the barrier during the process is not precisely controlled, the role of the barrier as a diffusion inhibitor could be questionable.

Numerical analysis of thermal effects in SOI MOSFET Flip-Chip packages: Multi-scale studies on isolated transistors and global simulations

We present numerical simulations of thermal phenomena in SOI MOSFETs flip-chip packages. We consider the effects of package environment on isolated transistors performing multi-scale Finite Elements thermal simulations. Furthermore, we perform a complete thermal analysis of a microchip in a flip-chip package. We build a robust Finite Elements model of a typical ten-level Back End of Line (BEoL) in order to evaluate the effects that metal interconnects of the BEoL have on local and global temperature elevation. In order to perform a multi-scale simulation, we compute equivalent thermal properties for composite components that we apply to the macroscopic model for obtaining coherent results. Homogenized values show that the conductivity of the BEoL is one order of magnitude higher in the lateral direction than in the vertical one, with values ranging between 50 - 100 W/mK laterally and between 1 - 5 W/mK in the vertical direction. Therefore, the spreading of heat takes place mainly laterally through metal lines. Results in the microscopic model confirm that heat flowing towards the heat sink passes mainly through metal interconnects. The hot spot temperature elevation is around 90 K for a transistor with gate length L of 30 nm and active width W of 0.5 μm, value that is lower than for the hot spot at wafer level in the same transistor. We analyze the impact of the density of metal interconnects on temperature elevation, deducing relative variations of up to 100% on the temperature of the first metal level. Macroscopic inspection of a typical 28 nm CMOS Flip-Chip product shows that copper pillars create a path for heat transfer, resulting in hot spots on the top of the Ball Grid Array (BGA) and cold areas at active level. The temperature difference at chip level is around 12 K, with values depending on the distribution of copper pillars and the thickness of the Silicon bulk. We analyze the impact of a variation in the pitch between copper pillars on the maximum temperature, verifying that a higher pitch causes a variation of up to 8 K on maximum temperature in extreme cases. We propose an accurate compact model that predicts the impact of copper pillars placement based on approximation of equivalent thermal properties. Finally, we deduce that, independently of the molding compound presence, increasing the Silicon bulk thickness causes a homogenization in the temperature map at chip level, as the temperature difference is around 12 K for a bulk of 110 μm decreasing to 4 K for a bulk of 770 μm.

Atomistic predictions of substrate orientation impact during SiGe alloys solid phase epitaxial regrowth

Coupled effects of substrate orientation and germanium concentration during silicon-germanium Solid Phase Epitaxial Regrowth (SPER) is analyzed through lattice kinetic Monte Carlo simulations. Atomistic events depending on the bonding environment allow to replicate the effects of alloying on SPER velocity of (100) substrates. The model is then used to draw predictions of the regrowth anisotropy in SiGe. Whereas Ge increase leads to a well-established SPER rate increase, whatever is the substrate orientation, moving away from (100) substrate orientation leads to a decrease of SPER rate caused by an unavoidable competition between the atomistic recrystallization configurations.

Cu/SiO 2 hybrid bonding: Finite element modeling and experimental characterization

Among the numerous ways to address 3D stacking of integrated circuits, a promising method is Cu/SiO2 hybrid bonding, which is the simultaneous metallic bonding of the interconnection pads and direct bonding of the dielectric surfaces. Prior to bonding, a chemical-mechanical polishing step is necessary, resulting in copper pads being slightly overpolished compared to the surrounding oxide regions (dishing effect). This effect, if too important, can prevent bonding and thereby lead to electrical connection failure between top and bottom parts. In order to better understand the involved phenomena and to perform virtual prototyping, a 3D finite element model for the thermal annealing of Cu/SiO2 hybrid bonded pads is presented, taking into account the dishing effect. In this work, the contributions to bonding of thermoelastic deformation and cohesive interactions are investigated, and the impact of pad shape on Cu-Cu interface closure during thermal annealing studied. In addition, a parametric study is conducted, in order to identify the most efficient design and process parameters to improve bonding quality.

Yield improvement and ramp-up to production of advanced CMOS technologies interconnects

Process complexity of advanced CMOS technologies interconnect increases continuously in the uninterrupted move towards miniaturization and verticalization. In the same time the window market of new more complex consumer products are shrinking faster and faster. This paper gives a comprehensive description of the most relevant and advanced methodologies and tools carried out to achieve quickly a yielding and reliable BEOL interconnect process in most advanced technologies.

Integration of a 3 level Cu-SiO/sub 2/ air gap interconnect for sub 0.1 micron CMOS technologies

Integration of three level of SiO/sub 2/ air gap has been successfully achieved in a complete CMOS copper interconnect scheme. SiO/sub 2/ air gap is demonstrated to be a reliable ultra low k for sub 0.1 /spl mu/m technologies with a well controlled dielectric constant below 2.