Sebastien Gallois-Garreignot

Thermal Effects of Silicon Thickness in 3-D ICs: Measurements and Simulations

This paper presents the impact of silicon thickness on the temperature and the thermal resistance in a 3-D stack integrated circuits. This paper uses electrical measurements thanks to embedded in situ sensors and numerical design of experiments (DOEs). The primary objective is to provide the sensitivity of modeling factors by analyzing the variance on the basis of Sobol indices through DOE. The results show a strong influence of the silicon thickness and of the position of the hot spots with respect to the sensors on the maximum temperature and the thermal resistance of the total stack. The boundary conditions, in particular the heat-transfer coefficient of the bottom surface of the wafer, are also identified as significant factors. Therefore, simulation results and measurement approaches are compared. The measurements are carried out with embedded in situ sensors in the bottom die at wafer level. The results show a significant increase in temperature while decreasing the silicon thickness.

Numerical analysis of thermo-mechanical and mobility effects for 28 nm node and beyond: Comparison and design consequences over bumping technologies

Abstract Thanks to finite elements simulation and dedicated post-processing routines, this paper explores stress induced mobility changes over three major bumping processes. A numerical comparative analysis over the assembly generations is carried out. In order to do so, models are built for solder flip chip, copper pillar flip chip and micro-copper pillar bumping. Design recommendations for MOSFET placement to include in conception tools are provided, which allow to ensure adherence to product specifications while technologies advance. It is demonstrated that stress effects on mobility are widely dependent on the integration flow, and transistor placements must be considered accordingly. Despite the fact that, qualitatively speaking, the generated stress states are quite similar for whole bumping schemes, the quantitative variations of each stress components in combination with the piezo resistive coefficients of silicon lead to distinct effective mobility variations. As a consequence, design rules and keep out zones can be optimized specifically for each assembly technology. More precisely, it is advised to avoid nMOS placement directly below the bump in flip chip devices, for which the mobility can be degraded by almost 5%. In these cases keep out zones must be considered. Reversely, in the case of 3DICs, the performances of nMOS are improved by more than 2% in that region, which means that no restriction is required and silicon area can hence be saved. As for the p type carriers, variability is sensitive to channel orientation rather than their location with respect to the bump: more precisely, the transport direction must be azimuthally oriented, and radially oriented pMOS are proscribed. Maximum variations of about ±5% are found for the copper pillar flip chip configuration. Thanks to a comprehensive analysis, FEoL designers will be able to integrate BEoL and packaging constraints during the conception phases of advanced semiconductor products.

Thermal correlation between measurements and FEM simulations in 3D ICs

This paper presents a comparison between electrical measurements, which are carried out with embedded in-situ sensors, and thermal numerical simulations. The objectives of this study are firstly to calibrate the Finite Element model by comparing the measurement results with those from simulations through a Design Of Experiments (DOE), and then to provide thermal recommendations on the studied parameters thanks to the calibrated numerical model. The primary objective of the DOE is to quantify the sensitivity of modeling parameters. Results show a strong influence of the silicon thickness, the convective heat transfer coefficient of the bottom surface, the thickness of the thermal insulation and the position of the hot spots relative to the sensors. The boundary conditions, particularly the heat transfer coefficient are also identified as significant parameters. Once the main factor set determined, the second objective of this study is to weight quantitatively the influence of key parameters. Finally, by providing a numerical and experimental comparison, this paper provides validated values of boundary conditions to be applied in the numerical simulations. These are considered to be the most difficult to obtain, while they have a huge influence on the simulation results, and this work allows to provide reliable thermal recommendations on designs to manage self-heating challenges.

Fracture phenomena induced by Front-End/Back-End interactions: Dedicated failure analysis and numerical developments

Abstract Related to Front-End/Back-End compatibility problematic, a systematic scheme to investigate and solve mechanical concerns is described: numerical study coupled with experimental failure analysis is proposed. Observations on Ball Grid Array (BGA) packages show that a reproducible failure mechanism appears within the low-k layers. Mechanical modeling is then used to reproduce and forecast this phenomenon. To define the most suitable method to be implemented, i.e. which combines accuracy and little arduousness, benchmark of two numerical failure criteria is performed: the widely known Cohesive Zone Method and an in-house developed Nodal Release Energy method. This latter has the higher easiness of use and implementation, especially in complex three dimensional architectures. Using this criterion, good correlation with the crack features experimentally observed is found near the die corner. Additional trends are drawn to depict and explain the crack behavior within the die. Finally, a trustful and benchmarked simulation frame, validated by experiments, brings key advantages for new product introductions, low cost development and optimized cycle time.

Strain engineering for bumping over IPs: Numerical investigations of thermo-mechanical stress induced mobility variations for CMOS 32 nm and beyond

In this paper, numerical investigations of the mechanical effect of the bumping process on the electrical performances of transistors are performed. This aims to forecast mobility changes and to provide guidelines on the design rules for MOSFET placements within the die. Hence, starting from thermo-mechanical simulations of the process, piezoresistive theory is employed to evaluate carrier speed variations. Insights are provided for both nMOS and pMOS types, and discussion is proposed regarding their relative effect of their location with respect to the bump. Comprehensive analysis is conducted on a typical case, and complemented by a design of experiments to explore the effects of the assembly layout. Results show that the bumping process induces significant stress values, which would be responsible for introducing electrical variability of several percents. As a consequence, care must be taken while defining transistor placement and the package layout should not be ignored. Readers will find suggestions for exclusion areas for IPs placements in flip-chip product, and trends for early phase of technology development.

Thermal behavior of stack-based 3D ICs

The 3D IC technology has attracted much interest in the recent past as a mean to efficiently improve performance and miniaturization of electronic integrated circuits (IC) [1]. The integration is based on three dimensional (3D) die stacking, connected thanks to Through Silicon Vias (TSV), μcopper pillars and large copper pillars. Although this approach offers several advantages in terms of electric features, the thermal management is widely identified as one of the key challenges [2]. The purpose of this study is to present a numerical model based on finite elements, to be calibrated and validated by experimental means (i.e. electrical in-situ and thermal IR measurements). In this paper, a presentation of our test chip (stacking, heaters and embedded sensors), the impact of various geometric parameters, the behavior of TSV around heated areas, and thermal properties of materials in the 3D stack-based will be presented. Our numerical model is composed of two chips stacked on a BGA. We use homogenized properties of TSV, Cu-Pillars (CP), μCP and BEOL. The best combination of geometrical (diameter, pitch) and technological (SiO2 and Silicium thickness, underfill properties) parameters in terms of thermal dissipation is extracted through design of experiments. We aim to know the internal thermal behavior despite the strong influence of poorly known boundary conditions. Finally, by proposing a whole numerical and experimental approach, this paper brings insights for early phase development of 3D ICs on self heating questions.

Investigations of Thermomechanical Stress Induced by TSV-Middle (Through-Silicon via) in 3-D ICs by Means of CMOS Sensors and Finite-Element Method

This paper aims at determining thermomechanical stress variations induced by annealed copper filled through-silicon via (TSV) in single crystalline silicon using metal-oxide-semiconductor (MOS) rosette sensors. These eight branches sensors were specifically designed and embedded in a 65-nm CMOS technology test vehicle. An in-house four-point bending tool was employed to calibrate and to extract the six independent piezoresistive coefficients. Through the piezoresistive relations, the stress tensor was evaluated by carrying out electrical measurements on wafer splits. A finite-element approach was also adopted to evaluate numerically the stresses and the expected mobility variations induced by TSV. According to this paper, a large variation of stresses (up to 100 MPa) in the sensor area was estimated, suggesting possible sensor design improvements to better accuracy. A good agreement was obtained between numerical and experimental results, except for the orthoradial component, which was found slightly compressive experimentally. Based on a critical analysis of the experimental-numerical methodology and results detailed in this paper, guidelines are drawn to get better accuracy through the improvement of MOS size and positions as well as recommendations regarding test strategy to overcome process variability. In the longer term, such improvements should lead to the definition of a comprehensive strategy for mechanical stress probing with in situ structures in advanced semiconductor products.

Chip/package interactions on advanced flip-chip packages: Mechanical investigations on copper pillar bumping

New customer demands for improved performance of ICs constantly require development of novel assembly processes. Hence, following the introduction of copper pillar bump, some Chip-package compatibility concerns are observed while processing, such as reflow or thermal cycles. In this paper, the mechanical behavior of the copper pillar is particularly studied. The effectiveness of a repassivation layer, namely polyimide (PI), to lower the stress within pad structure is assessed experimentally thanks to dedicated test vehicles. Results show that the polyimide introduction is not always relevant since it induceds the lowest yield. The typical observed failure modes are described. In order to get a better understanding of the involved mechanisms, Finite Element simulations are performed. Numerical results show that the Copper/Aluminum interface is one of the main criteria to assess the stress field within the pad. By introducing the polyimide layer, the copper pillar section is reduced and then, leads to higher stress concentration within the pad structure. Then, the effect of the polyimide is compared for two bump configurations: solder and copper pillar. It is shown that in case of solder bump, the repassivation layer is much more stressed and allows to limit the stress within the interconnect stack compared to the unpassivated configuration. Distinct behavior is then observed between solder and copper pillar bumps concerning the PI implementation. At last, the effect of fine pitch bumping is investigated and any interactions are found for the considered values. Thanks to these investigations, differences between solder bump and copper pillar bumps are shown and the needs of dedicated developments for copper pillar bump integration are thus underlined.

Thin films interfacial adhesion characterization by Cross-Sectional Nanoindentation: Application to pad structures

The feature size reduction on IC chips following Moores law leads to great integration challenge. Among others, the mechanical integrity of pad structures is particularly critical. However, to find suitable containment actions remain tricky, and a better knowledge and characterization of interfaces are then mandatory to face these problems. The Cross-Sectional Nanoindentation (CSN) is a novel method of mechanical characterization, developed by Sanchez et al. [1]. With such method, various interfaces can be characterized, at the micrometer level, in terms of adhesion energy. Its advantages compared to the well-known 4pt bending technique are numerous: a simple and fast sample preparation, direct observation of the crack path, etc. In this paper, the CSN technique is applied to discriminate and characterize the interfaces which compose a typical wire bond pad structure. More precisely, Inter-Metal Dielectric/Metal stacks, describing a pad level are tested by the mean of CSN. The exact failed interface is then determined by SEM views. However, in order to compare the interface to each others, the adhesion energies need to be known. Due to the plastic deformation of the metal during the test, Finite Element Method (F.E.M.) is required. A 2D axisymmetric model, described in [2], is used to reproduce the test. Each stack with their characteristics is simulated and an energetic quantity is calculated. Based on these values, the interfaces are finally ranked according to their mechanical reliability. Additional insights and novel findings from the state of the art are also discussed concerning both experimental and numerical aspects of the method. At last, the ability to discriminate pad structures straightforwardly by CSN is also studied. Crack behavior is investigated by S.E.M. views and a discussion is proposed concerning the most relevant criterion. Future developments concerning this method are finally described.

Chip-package interactions: Some investigations on copper/Low-k interconnect delaminations

The introduction of brittle dielectric materials, and the feature size decrease of IC chips to follow Moores law, are well known to pose great integration challenges. In this paper, a 3D fully parameterized finite elements of a ball grid array package model is built and thermo-mechanical stress produced during package operations is evaluated. That aims to address FE-BE compatibility concerns. Thanks to multi level and energy based post processing methods, both analysis at the package and interconnect levels are carried out. Localized evaluation of the crack propagation likelihood into the low-k stack is performed, and several results are provided: Localisation of the delaminated interface and the particular effects of the glue fillet geometry are specially studied. Discussion on failure criteria is also proposed in order to bring inputs on dielectric damaging phenomena in advanced semiconductor products. The sensitivity to shear modes, contrary to compressive one is highlighted. On the other hand, a drastic rise of the fracture risk is suspected with highest values of the glue fillet, which might lead to delamination of the bottommost IMD layers. Possible applications of this work are the early phases of technology developments and product crisis solving.