Roger A. Cline

A successful HBM ESD protection circuit for micron and sub-micron level CMOS

Abstract A successful ESD protection circuit depends on a clear understanding of the process parameters and design rules of a given fabrication process. This work will show an ESD protection scheme that protects CMOS well as minimum feature sizes ranging from micron to sub-micron scales. The primary protection device utilizes an SCR structure available from a N-Well CMOS process in conjunction with a series N-Well resistor. ESD immunity of > 2kV has been demonstrated on state of the art ASIC arrays using these structures.

Formation and suppression of a newly discovered secondary EOS event in HBM test systems

A previously undetected trailing pulse from HBM testers was found to create unexpected gate oxide failures on new technologies. This secondary pulse, which is EOS in nature, is caused by the discharge relay and the parasitics of the charge circuit. This paper investigates this critical phenomenon and establishes the tester improvements to safely suppress the trailing pulse effects.

A new I/O signal latchup phenomenon in voltage tolerant ESD protection circuits

We report for the first time a new type of unexpected latch-up phenomenon that can occur in deep sub-micron technologies with the required implementation of voltage tolerant ESD protection circuits. In contrast to the well known Standard latchup, this new latchup, dubbed Signal Latchup, becomes evident only through the interaction from neighboring I/O pins. The issues involved with this latchup effect and the subsequent trade-off with ESD are presented in detail. A new latchup specification is also proposed.

Development of substrate-pumped nMOS protection for a 0.13 μm technology

A methodology is presented for improved process and circuit development of substrate-pumped nMOS protection. ESD process development is accelerated by applying factor analysis to completed non-ESD experiments. Factor analysis is complimented by a straightforward diagnosis of nMOS snapback. This approach enabled verification of two process solutions, including a novel method, in one fab cycle-time. HBM data that shows the Substrate-Pumped nMOS can provide dramatically higher protection than estimated from conventional It2 measurements. This motivates improved ESD circuit development. The nMOS clamp transistor is characterized as an actively biased LNPN, which is how it is used in a Substrate-Pumped protection circuit. A system-oriented approach to circuit development is described that is based upon empirical characterization of well-defined circuit components under conditions approximating ESD.

Latchup in voltage tolerant circuits: a new phenomenon

Abstract The semiconductor industry relies on latchup testing of integrated circuits (ICs) to detect and prevent catastrophic failures under extreme conditions. The test is mandatory to ensure that parasitic components do not adversely affect the normal behavior of the ICs, especially in CMOS technologies. This phenomenon has been well documented over the years. For the newer technologies with lower power consumption (supplies in the range of 1–2 V), one might consider them to be less susceptible to latchup. However, the presently designed ICs with nanometer technologies continue to require “high voltage” interface compatibility through applications such as PCI, etc. Moreover, some of the IC pins are exposed to much higher level ESD stresses (IEC test) due to pin connections between systems. As a consequence, latchup has become more difficult while manifesting itself into new scenarios including system level ESD effects. This paper first reviews the background of the latchup phenomenon and then introduces a new form of latchup called Signal Latchup that could very well be a critical issue for the newer IC applications where high voltage compatibility is required. In this same context, System Level ESD latchup is also described. This paper gives the background of CMOS latchup, followed by a description of the latchup initiation and latchup immunity test methods. The system board reliability is discussed. The new Signal Latchup phenomenon is introduced. An illustration of Signal Latchup occurring in voltage tolerant circuits and the design improvement to overcome this are presented in detail. The impact of process technology on these new latchup effects is evaluated and the system ESD latchup is presented. The Signal Latchup and ESD system Latchup testing is covered. Finally, the conclusions are given.