Sungjun Chun

Modeling and transient simulation of planes in electronic packages

This paper presents a modeling and simulation approach for ground/power planes in high speed packages. A plane pair structure is first characterized in terms of its impedance (Z) matrix at arbitrary port locations in the frequency domain. This solution is then extended for multiple plane pairs under the assumption that skin effect is prominent at higher frequencies causing isolation between the layers. Since the solutions are in analytical form, the frequency and transient response can be computed efficiently requiring small computational time. To develop spice models, equivalent circuits are constructed using resonator models with passive elements using model order reduction methods. This paper also discusses a method for incorporating decoupling capacitors into the plane models. The simulation results show good correlation with measured data.

Modeling of simultaneous switching noise in high speed systems

Simultaneous switching noise (SSN) has become a major bottleneck in high speed digital design. For future systems, modeling SSN can be complex: due to the thousands of interconnects that need to be analyzed. This is because a system level modeling approach is necessary that combines the chip, package and board level interactions. This paper presents an efficient method to model the SSN for high speed systems by developing circuit models for the planes and interconnections that can be combined using superposition theory. This approximation is valid at frequencies where skin effect is dominant. Simulation results are compared with the measurements on a test vehicle, verifying the validity of the method. In addition a system has been simulated to compute SSN, showing the application of this method for complex systems.

Simultaneous switching noise suppression for high speed systems using embedded decoupling

High performance computing systems are driving towards higher clock speeds, more switching circuits, and lower operating voltages. Simultaneous switching noise (SSN) will greatly affect signal integrity in such complex future mixed signal systems. It has been reported that in addition to inductance effects, power plane bounce also becomes a critical factor for packages containing many power and ground vias in parallel. Discrete surface mount capacitors are currently being used by designers to suppress noise. As part of the System on a Package (SOP) concept being developed at the Packaging Research Center (PRC), Georgia Tech, a test vehicle to demonstrate the suppression of SSN using embedded decoupling capacitors is being implemented. This test vehicle uses thin film sequential buildup technology on a low-cost organic platform incorporating polymer-ceramic nanocomposite dielectrics. The design rules for the test vehicle were developed using SOP substrate materials and processes; furthermore, Ansoft along with Matlab were used to model the microstrip transmission lines. The layout was done using Cadence Advanced Package Designer (APD) and output into Gerber format for fabrication. The current test vehicle uses a 300 mm /spl times/300 mm high T/sub g/ FR-5 base substrate with four metal layers on each side. Photoimageable epoxy dry films of 25 /spl mu/m and 75 /spl mu/m thickness were used as the low k (3.4-3.9) sequential build-up dielectric. A novel photoimageable polymer ceramic nanocomposite material developed at the PRC was used for the high k (25-50) thin films. Low cost materials and large area processes were used for the substrate fabrication including dry film printed wiring board (PWB) photoresists, vacuum lamination and spin/meniscus coating for dielectric deposition, full-field UV lithography, and electroless and electrolytic copper metallization. Simulations confirm that the SSN will be suppressed by a factor often when using the high k material as the capacitor dielectric. This paper presents the design, fabrication and validation of embedded decoupling for SOP technology.

A methodology for the placement and optimization of decoupling capacitors for gigahertz systems [CMOS VLSI]

This paper discusses a method for computing the effect of decoupling capacitors on the power delivery system for gigahertz packages and boards. A fast and accurate computational method is presented that can be used to estimate the amount of decoupling required, the type of capacitor to be used and its location (on-chip, package or board).

Model to hardware correlation for power distribution induced I/O noise in a functioning computer system

The Power Distribution System (PDS) for Input/Output (I/O) drivers in high-speed computer system is often separated from that for the microprocessor core. Modern computer systems contain hundreds of driver I/Os, decoupling capacitors and signal transmission lines that carry the data between chips. Simultaneous switching of these hundreds of drivers causes noise, i.e., voltage fluctuation on the power supply rail, which causes signal integrity problems of the data on the signal transmission lines. This paper discusses measurements of noise due to driver I/O switching in a high speed functioning computer system. The transfer impedance of a PDS was measured and noise of the functioning PDS in both frequency and time domain was measured. This paper presents an efficient methodology to model these noise waveforms. Modeling results have shown good agreement with measurements, demonstrating the application of the methodology to complex and realistic boards. Reduction of I/O switching noise through thin dielectric was also simulated using the modeling method presented.

Physics based modeling of simultaneous switching noise in high speed systems

Simultaneous Switching Noise (SSN) has become a major bottleneck in high speed digital design. For future systems, modeling SSN can be complex due to the thousands of interconnects that need to be analyzed. This is because a system level modeling approach is necessary that combines the chip, package and board level interactions. This paper presents an efficient method to model the SSN for high speed systems by developing circuit models for the planes and interconnections that can be combined using superposition. This approximation is valid at frequencies where skin effect is dominant. Simulation results are compared with the measurements on a Test Vehicle, verifying the validity of the method.

Capturing via effects in simultaneous switching noise simulation

This paper presents a method for including via effects in modeling simultaneous switching noise (SSN). Models for interconnections and multi-layered planes have been developed and combined using superposition based on skin depth approximation to capture the return current effect due to via transitions. Measurements on active board containing the drivers, transmission lines, vias and planes have been conducted. The modeling approach has been correlated with measurements, showing the validity of the method. The modeling method has been extended and applied to large size systems to model the power supply fluctuations due to via transitions.

Electromagnetic modeling and hardware measurements of simultaneous switching noise in high speed systems

This paper discusses the modeling of simultaneous switching noise in high speed systems. Various methods have been presented and the accuracy of these methods has been verified through measurements in both the frequency and time domain. These measurements include experimental test vehicles and functional products.

Comparison of methods for modeling ALAN's power plane structure

This paper compares three methods for modeling power plane structures. The power plane structure that was analyzed was given by Dr. Albert Ruehli and Prof. Andreas Cangellaris, hence the acronym ALAN. The methods have been compared in terms of accuracy and computation time. The advantages of each method have also been discussed.

Application of wavelets and generalized pencil-of-function method for the extraction of noise current spectrum and simulation of simultaneous switching noise

In high performance systems, the voltage fluctuation noise caused by the simultaneous switching of circuits is an important concern in relation to signal integrity and radiated emission related issues. For proper design of the Power Distribution System the noise current is required as an input for the simulation of the simultaneous switching noise. This paper proposes a measurement based approach to estimate the noise current spectrum in a functioning computer system. Its also discusses a method for extracting the current signature needed to simulate switching noise in the system. The proposed approach is tested on a high speed functioning computer system from Sun Microsystems. Using the current source developed, simultaneous switching noise in the core power distribution network of the system has been simulated with good accuracy.