Roger W. Cheek

Ultra-Thin Phase-Change Bridge Memory Device Using GeSb

An ultra-thin phase-change bridge (PCB) memory cell, implemented with doped GeSb, is shown with < 100muA RESET current. The device concept provides for simplified scaling to small cross-sectional area (60nm2) through ultra-thin (3nm) films; the doped GeSb phase-change material offers the potential for both fast crystallization and good data retention

Novel One-Mask Self-Heating Pillar Phase Change Memory

A novel Pillar phase change memory based on fully integrated test arrays in 180nm CMOS technology has been successfully fabricated. A current-confining Pillar structure leads to a self-heating at the center of the chalcogenide layer, and needs only one additional mask level for its fabrication. Switching characteristics with write currents less than 900muA at 75nm diameter and multilevel operation are reported

Nanoscale electronic synapses using phase change devices

The memory capacity, computational power, communication bandwidth, energy consumption, and physical size of the brain all tend to scale with the number of synapses, which outnumber neurons by a factor of 10,000. Although progress in cortical simulations using modern digital computers has been rapid, the essential disparity between the classical von Neumann computer architecture and the computational fabric of the nervous system makes large-scale simulations expensive, power hungry, and time consuming. Over the last three decades, CMOS-based neuromorphic implementations of “electronic cortex” have emerged as an energy efficient alternative for modeling neuronal behavior. However, the key ingredient for electronic implementation of any self-learning system—programmable, plastic Hebbian synapses scalable to biological densities—has remained elusive. We demonstrate the viability of implementing such electronic synapses using nanoscale phase change devices. We introduce novel programming schemes for modulation of device conductance to closely mimic the phenomenon of Spike Timing Dependent Plasticity (STDP) observed biologically, and verify through simulations that such plastic phase change devices should support simple correlative learning in networks of spiking neurons. Our devices, when arranged in a crossbar array architecture, could enable the development of synaptronic systems that approach the density (∼1011 synapses per sq cm) and energy efficiency (consuming ∼1pJ per synaptic programming event) of the human brain.

Programmable via Using Indirectly Heated Phase-Change Switch for Reconfigurable Logic Applications

A novel concept for a programmable via using an indirectly heated phase-change switch is proposed and fabricated successfully. In this device concept, circuits associated with the programmable via are decoupled from the configuration circuits by using an independently contacted heater electrode. We demonstrate the prototype device in a standard 180-nm CMOS copper back-end technology.

A high performance phase change memory with fast switching speed and high temperature retention by engineering the Ge x Sb y Te z phase change material

Phase change memory has long suffered from conflicting material properties between switching speed and thermal stability. This study explores the engineering of GeSbTe ternary alloys along an isoelectronic tie line and the Ge/Sb2Te3 tie line with the hope of finding a high performance material. Our efforts resulted in a new material that considerably outperforms the conventional GST-225. The switching speed is similar to undoped GST-225, with ∼ 30% lower reset current, and nearly 100°C higher Tx, thus much better thermal stability. The promising properties of this new material are demonstrated in a 128Mb chip and tested both at wafer level and as packaged dies. These devices showed 1E8 cycling endurance and withstood 190 °C testing.

A low power phase change memory using thermally confined TaN/TiN bottom electrode

Application of phase change memory (PCM) has been limited by the high power required to reset the device (changing from crystalline to amorphous state by melting the phase change material). Utilizing the poor thermal and electrical conductivity of TaN we have designed a simple structure that thermally insulates the bottom electrode and thus drastically reduces the heat loss. A 39nm bottom electrode with a TaN thermal barrier and 1.5nm of TiN conductor has demonstrated 30µA reset current, representing a 90% reduction. The benefit of thermal insulation is understood through electrothermal simulation, and the benefit is demonstrated in a 256Mb test chip. The low reset current also improves the reliability and excellent cycling endurance >1E9 is observed. This low power device is promising for expanding the application for PCM.

On the dynamic resistance and reliability of phase change memory

A novel characterization metric for phase change memory based on the measured cell resistance during RESET programming is introduced. We show that this dasiadynamic resistancepsila (Rd) is inversely related to the programming current (I), as Rd = [A/I] + B. While the slope parameter A depends only on the intrinsic properties of the phase change material, the intercept B also depends on the effective physical dimensions of the memory element. We demonstrate that these two parameters provide characterization and insight into the degradation mechanisms of memory cells during operation.

Understanding amorphous states of phase-change memory using Frenkel-Poole model

A method based on Frenkel-Poole emission is proposed to model the amorphous state (high resistance state) in mushroom-type phase-change memory devices. The model provides unique insights to probe the device after amorphizing (RESET) operation. Even when the resistance appears the same under different RESET conditions, our model suggests that both the amorphous region size and the defect states are different. With this powerful new tool, detailed changes inside the amorphous GST for MLC operation and retention tests are revealed.

Endurance Improvement of Ge2Sb2Te5-Based Phase Change Memory

We describe a cycling failure mode in Ge 2 Sb 2 Te 5 -based phase change memory, based on density difference of GST in different phases and the SET/RESET thermal operations. Voids that develop and merge with each other within GST programming volume after cycling eventually lead to cell failure. By adding suitable amount of doping material into GST, we are able to delay this void formation process and to significantly improve the cell endurance to more than 10 9 cycles.

Mechanisms of retention loss in Ge 2 Sb 2 Te 5 -based Phase-Change Memory

Data retention loss from the amorphous (RESET) state over time in Phase-Change Memory cells is associated with spontaneous crystallization. In this paper, the change in the threshold voltage (VT) of memory cells in the RESET state before and after heating is used as a probe into the nature of the retention loss mechanisms. Two mechanisms for the retention loss behavior are identified, responsible for the main distribution and the tail distribution, respectively. Experimental results suggest that (i) an optimized RESET operation produces a fully amorphized Ge2Sb2Te5 (aGST) active region, with no crystalline domains inside, (ii) cells in the tail distribution fail to retain their RESET state due to spontaneous generation of crystallization nuclei and grain growth, and (iii) cells in the main distribution fail due to grain growth from the amorphous/crystalline GST boundary, instead of nucleation within the active region.