Rohan Mandrekar

Link analysis and design of high speed storage buses in backplane and cabling environments

This paper discusses electrical performance and design aspects of SAS (Serial Attached SCSI) link channels in various server storage system configurations through modeling and simulation analysis in frequency and time domain. The signal loss behaviors are investigated in two interconnect structures, internal SAS links in host enclosure backplanes and external SAS links in cabling environment. While signals in external SAS links experience excessive loss through lengthy cables in meters, those of internal SAS links are impaired by multiple discontinuities of board components over less than a couple of feet of PCB routing though largely dependent of system design. While eye closure is parallel to loss magnitude in general, higher degree of discontinuities exhibited in frequency loss behavior of channels result in more eye closure despite lower loss magnitude reducing design space budget and the impact is greater with higher data rates.

Distributed On-chip Power Supply Noise Characterization of the Cell Broadband Engine

Noise characterization of the 65 nm multicore Cell Broadband Enginetrade (Cell/B.E.)* processor was performed using highly configurable workloads and selective stimulation of identical cores to study noise distribution throughout the chip. On-chip power supply noise propagation velocity and attenuation were found to be influenced by chip/package resonance in the power distribution system. Hypothesis for this phenomenon is proposed.

Minimizing crosstalk noise in vias or pins by optimizing signal assignment in a high-speed differential bus

Vias in packages and boards, land-grid-array pins, and connector pins introduce significant crosstalk in high-speed differential buses. There are many possible differential signal assignments in those areas that have very different electrical performance. This paper proposes and demonstrates an efficient method to find a large number of possible assignments and assess them to obtain an optimal assignment with the best performance.

Power supply noise simulation considering dynamic effect of on-chip current

This paper describes a technique to analyze the dependence of on-chip switching current on power supply voltage and temperature, and how to implement that in power supply noise simulations. It is shown that this on-chip dynamic effect can introduce significant damping to the otherwise passive chip/package/board power supply network

Packaging the Cell Broadband Engine microprocessor for supercomputer applications

The Cell Broadband Enginetrade (Cell BE) processor initially designed for high-end consumer electronics, has been enhanced by IBM for supercomputer applications. The enhancements to the chip also necessitated the design and development of a new package. The modifications to the chip included replacement of the 3.2 Gb/s XDR interface with a 800 Mb/s DDR2 interface of equal bandwidth. This required the addition of several hundred chip-level connections (C4s) and package BGA balls. Incorporating this and other enhancements to the chip resulted in a ~20% larger chip and a larger and more complex package. Additional noise from this large memory interface also drove decoupling requirements that necessitated mounting capacitors on both the top and bottom sides of the package. This paper describes the design of this new package as well as the analysis and characterization techniques used to address the packaging concerns outlined above. It includes a comprehensive noise analysis as well as a thorough characterization of the DDR2 interface in the final prototypes. The paper also outlines the design and analysis of the power distribution to the various voltage domains on the chip. Along with electrical design and performance, the paper also includes finite element modeling of the mechanical stresses resident in this FCPBGA package. Finally, the concluding portions of the paper will discuss the trade-offs between electrical performance and mechanical stability, reliability and relative cost.

Techniques and considerations for verification of model causality

High data switching rates of todays computer architecture continue to intensify the need for transmission line modeling accuracy. As these data rates exceed hundreds of megahertz and the physical complexity of the transmission channel increase, it may no longer be sufficient to ensure only the frequency dependency of channel models. Rather, the model developer must guarantee the model response is passive and causal. This is of particular interest given that non-causal models may not allow convergence or yield accurate channel loss within industry-standard tool suites, even though its response may yield reasonable correlation to measured scattering parameters. Therefore, model developers must understand how the model creation, checking and simulation tools work together to ensure validity of transient simulations. Commercially-available tools exist that provide numerical and visual interpretation of causality compliance (or violation) for any given touchstone model. It is critical, however, for the model developer to understand the verification process used within a chosen tool suite and how to interpret results. Moreover, model developers must know how model frequency content, step size, length and other parameters may impact a checking tools ability to accurately flag causality violations. As a result, the developer must have an in-depth understanding of the correlation between model content and causality error reporting, whether or not violations raise real concerns and if so, how they may impact the results obtained from the system-level simulation methodology. This paper will discuss the interaction between the model development process, the ability to verify model causality and the impact at the link or system-level as a result of non-causal models or inaccurate interpretation of causality-checking verification tools.

Method to determine optimum equalization for maximum eye in high-speed computer system

With increasing demand on higher performance for I/O links, equalization in transmitters and receivers has been identified as a critical contributor that can improve the opening of the eye. This paper describes a method to optimize the equalization using zeroforcing to maximize I/O performance and its application to a realistic high-speed functioning system. Both hardware characterization and simulation results are provided to validate the method discussed in the paper.

Simulation of worst case switching noise on a DDR2 interface

This paper describes a new technique to simulate worst case simultaneous switching noise on a DDR2 interface. The paper focuses on how the impedance response of the power distribution network can be used in determining an excitation pattern that results in the worst case switching noise on the interface.

Switching regulator noise coupled onto high speed differential links

Modern PCBs are increasingly subjected to real estate constraints. Often tradeoffs are made between ideal signaling conditions and placement feasibility. Traditional analysis of high speed signals has focused on the effects of through-channel characteristics such as insertion loss, return loss, transmitter/receiver equalization, and crosstalk due to adjacent signals of the same bus. This paper presents an issue in preproduction hardware in which a switching regulators placement directly led to degraded margin in nearby high speed serial links via noise coupling. The phenomenon was characterized in a lab setting and subsequent hardware revisions implemented an isolation technique that proved highly effective.

Driver design for DDR4 memory subsystems

As DDR4 continues to move from the design phase towards implementation, several challenges have been identified to successfully implement this high performance memory architecture for next generation systems. This paper investigates driver design selection for DDR4 systems. The paper studies the pros and cons of three driver design types namely: standard, pre-emphasis, and de-emphasis on typical net topogies of 1DPC (DIMM per channel) and 2DPC operated at 2400MT/s. For each driver type the impact of source termination on performance and power saving capability is discussed. Since the effects associated with different driver designs can be best understood in the time domain this paper uses behavioral models created in the SPICE format for simulations.