Rohit Pal

A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications

Band-gap engineering using SiGe channels to reduce the threshold voltage (VTH) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafers for SOC applications has unique challenges like the oxidation rate differential with silicon, defectivity and interface state density in the unoptimized state, and concerns with Tinv scalability. In overcoming these challenges, we show that we can leverage the superior mobility, low threshold voltage and NBTI of cSiGe channels in high-performance (HP) and low power (LP) HKMG CMOS logic MOSFETs with multiple oxides utilizing dual channels for nFET and pFET.

Variation improvement for manufacturable FINFET technology

This works examines the sources of electrical variation for FinFET technology based on silicon data from 90nm contacted poly pitch, dual-epitaxy, and RMG (replacement metal gate) transistor. A simple statistical model is used to predict electrical variation based on physical variation that can be measured much earlier in the processing flow. The model is also used to define specification and control limits for physical variation to support the electrical variation specified in SPICE models. Gate stack, Junction, and Gate height variation are identified to be the key contributors to threshold voltage variation for FinFET technology. A case study is also presented on controlling gate height to the desired specification limits by improving across chip, within wafer, wafer to wafer, and lot to lot variation at multiple process steps.