Rolf Stephan

Advanced SOI CMOS transistor technologies for high-performance microprocessor applications

We present an overview of partially-depleted silicon-on-insulator (PD-SOI) CMOS transistor technologies for high-performance microprocessors. To achieve a “high performance per watt” figure of merit, transistor technology elements like PD-SOI, strained Si, aggressive junction scaling, and asymmetric devices need hand-in-hand development with multiple-core and power-efficient designs. These techniques have been developed, applied, and optimized for 45nm SOI volume manufacturing at GLOBALFOUNDRIES in Dresden. To enable further transistor scaling to 32nm design rules, high-K metal-gate (HKMG) technology is key. Gate-first and replacement-gate HKMG integration as well as future strained Si technologies like strained silicon directly bonded on SOI and embedded Si:C are discussed.

Comparison of MOCVD- and ALD-Deposited

For the first time, HfZrO4 dielectrics deposited with metal-organic chemical vapor deposition (MOCVD) as well as atomic layer deposition (ALD) have been investigated as high-k gate dielectric for 32-nm high-performance logic SOI complementary metal-oxide-semiconductor devices in this letter. The composition of the HfZrO4 films has been analyzed in detail by atom probe tomography, Rutherford backscattering spectrometry, and X-ray photoelectron spectroscopy. Optical inline measurements and electrical parameters such as gate leakage current, capacitance equivalent thickness, threshold voltage, and performance as well as reliability data have been taken into account to directly compare both deposition methods. All parameters indicate a comparable behavior for MOCVD and ALD. Therefore, MOCVD has been demonstrated to be a promising alternative to ALD in high-volume manufacturing.