Lutz Herrmann

Reduced Parameter Fluctuation with Laser and Flash Lamp Anneal for 65nm Volume Production

Process parameter fluctuations have a strong impact on functionality and performance of CMOS logic circuits and memory cells. Tight control of transistor gate length and final anneal temperature are equally important. We have developed a strategy to monitor these fluctuations which takes into account the full complexity of advanced microprocessors with large cache cell areas. This paper shows that reducing the anneal temperature reduces the parameter fluctuations. Transistor performance degradation at reduced temperatures can be compensated by using advanced annealing techniques like Laser or Flash lamp anneal. These techniques do not result in additional parameter fluctuation.

Influence Of Energy Contamination At S/D‐Extension Dopant Implantation Using Ultra Fast Annealing

Ion implantation at ultra low energies (<1keV) using deceleration of ions adjacent to the wafer surface appear to show energy contamination based on process parameters or design of the beamline of the implanter. Previously energy contamination was overwhelmed by diffusion of dopants when using soak or spike RTA processes. Use of ultra fast anneal techniques (e.g. flash/laser) for ultra shallow junction formation provides diffusion less activation of implanted dopants. Thus energy contamination is becomming a severe issue for precisely positioning pn‐junctions. By use of deceleration modes, front of the wafer, fractions of the dose penetrate the wafer at non‐decelerated energy and introduce undesired move of the junction depth. The fraction of decelerated to non‐decelerated ions typically needs to be less than ∼0.1% so that those amounts will not influence device parameters.