Ronald A. DellaGuardia

New ESCAP-type resist with enhanced etch resistance and its application to future DRAM and logic devices

This new photoresist system extends the capability of the ESCAP platform previously discussed. (1) This resist material features a modified ESCAP type 4-hydroxystyrene-t-butyl acrylate polymer system which is capable of annealing due to the increased stability of the t-butyl ester blocking group. The resist based on this polymer system exhibits excellent delay stability and enhanced etch resistance versus previous DUV resists, APEX and UV2HS. Improved stabilization of chemically amplified photoresist images can be achieved through reduction of film volume by film densification. When the host polymer provides good thermal stability the soft bake conditions can be above or near the Tg (glass transition) temperature of the polymer. The concept of annealing (film densification) can significantly improve the environmental stability of the photoresist system. Improvements in the photoacid generator, processing conditions and overall formulation coupled with high NA (numerical aperture) exposure systems, affords linear lithography down to 0.15 micrometer for isolated lines with excellent post exposure delay stability. In this paper, we discuss the UV4 and UV5 photoresist systems based on the ESCAP materials platform. The resist based on this polymer system exhibits excellent delay stability and enhanced etch resistance versus APEX-E and UV2HS. Due to lower acrylate content, the Rmax for this system can be tuned for feature-type optimization. We demonstrate sub-0.25 micrometer process window for isolated lines using these resists on a conventional exposure tool with chrome on glass masks. We also discuss current use for various device levels including gate structures for advanced microprocessor designs. Additional data will be provided on advanced DRAM applications for 0.25 micrometer and sub-0.25 micrometer programs.

Fabrication of 64-Mb DRAM using x-ray lithography

This paper describes results achieved from the fabrication of 64Mb DRAM chips using x-ray lithography for the gate level. Three lots were split at the gate level for exposure with either Micrascan 92 at IBMs Advanced Semiconductor Technology Center (ASTC) or x-ray at the Advanced Lithography Facility (ALF) containing a Helios super-conducting storage ring and a Suss stepper. The x-ray mask was fabricated at MMD (Microlithographic Mask Development Facility) as a two-chip mask containing one chip which had zero defects. To achieve adequate overlay performance between the x-ray exposed gate level and previous optically- printed levels, the mask was fabricated with an intentional magnification correction. The alignment scheme for both Suss and Micrascan was first order to an ASM zero level, and second order to each other. Results from the first lot show 90% of the chips tested achieved a +/- 140 nm target for the Suss to Micrascan overlay. Critical dimension control (across wafer and across chip) was measured and found to be comparable between Suss and Micrascan. Electrical performance was comparable to the optical wafers. Chips were fabricated with zero defects in many of the 1 Mb segments. There were also x-ray fabricated chips which demonstrated 63 Mb addressable bits.

X-ray transmission through low atomic number particles

Abstract Defect printability studies have been carried out using low atomic number particles mounted on thin silicon membranes. Transfer of the particle image to a resist-coated wafer was accomplished using synchrotron radiation from the VUV electron storage ring at Brookhaven National Laboratory and subsequent resist development. Residual resist images resulting from the particles on the membrane were measured with an SEM. A semi-empirical model has been developed that can approximately predict the size of the printed image on the wafer. Data is presented which shows that over-development of the photoresist, which removes the residual particulate images, can be achieved while maintaining exceptional line-width control in x-ray lithography.

BEOL lithography for early development at the 65-nm node

This paper will present results obtained during the early development of a lithography process to meet the requirements of the 65 nm node in the BEOL. For the metal levels, an IBM/JSR jointly developed trench level resist was characterized and implemented. Resist image profile, process window, through pitch performance, image shortening and the effect of illumination conditions are discussed. Results from focus - exposure monitor (FEM) wafers are shown which were characterized for minimum resolution, process window and electrical continuity through a maze structure. For the via levels, results from another IBM/JSR jointly developed resist with high resolution and process windows are described. Process windows for nested and isolated vias are given, as well as results showing the improvement in process window and resolution due to the ARC etch. The results also include FEM measurements showing the electrical continuity through simple via chain structures versus the dimension of the via.

Methods for comparing contact hole shrinking techniques with 248-nm single layer and bilayer photoresists

Several contact hole shrinking techniques have been discussed in the literature recently. Two notable techniques; Resolution Enhancement Lithography Assisted by Chemical Shrink (RELACSTM) and Resist Flow Process (RFP) were investigated in conjunction with several commercially available high activation energy chemically amplified materials and one bilayer material. During the course of this study the unique set of advantages along with the inconveniences associated with each technique were explored. It was not only the lithographic attributes of each technique that were of interest, but also characteristics that would effect manufacturability. To that end, experiments were designed so that standard statistical techniques could be employed at the data analysis stage. The attributes of interest were the amount and control of shrinkage, nested and isolated feature bias, process window comparisons, and line edge roughness. It will be shown how several of theses attributes are directly related to manufacturing issues such as lot-to-lot repeatability and linewidth variations across the wafer.

193 lithography and RELACS processing for BEOL lithography

This paper presents data obtained in developing a process using 193 nm lithography and the RELACS contact hole shrink technique. For the line/space levels, process windows showing resist performance using chrome on glass masks are presented. Data showing feature size linearity and the requirements for optical proximity correction (OPC) are presented. Some of the OPC trends observed are discussed and compared to results obtained using 248 nm lithography. Image shortening data also compares the results obtained in 193 and 248 lithography. Etch results for the new 193 resists are given and show the etch resistance of this relatively new class of photoresist materials. For contact hole and via levels, results using 193 lithography and COG masks show the importance of the mask error enhancement factor (MEEF), print bias and resolution. Due to the relative immaturity and performance of contact hole resists for 193 lithography, Clariants RELACS process was investigated with 248 nm resists. In this process contact holes are printed larger than required and then reduced to the desired size by a chemical shrink process. Results obtained with 248 lithography using state of the art resists and phase shift masks are discussed. It was found that 140 nm contact holes with at least 0.5 micrometer depth of focus could be obtained. Cross sections and process windows are shown.

All-Wet, Metal-Compatible High-Dose-Implanted Photoresist Strip

An all-wet process based on a novel chemistry has been developed to enable the removal of high-dose implanted photoresist in the presence of exposed metal layers and other materials typical of advanced gate stacks.

193-nm lithography and resist reflow for the BEOL

This paper presents data obtained in developing a lithography process for the metal and via levels using a first generation 193 nm stepper and first generation 193 nm photoresist. For the line/space levels, process windows obtained using chrome on glass (COG) and phase shift masks are presented. The effect of print bias (wafer - mask dimension) on process window is shown. At 280 nm pitch, process windows for COG and phase shift masks are compared. When using a phase shift mask to print 245 nm pitch, thinner resist is shown to increase the process window. Results are shown for printing 245 nm pitch with a COG mask. For contact hole and via levels, a resist reflow process was investigated with the same resist used for the line/space levels. In this process contact holes are printed larger than required and then reduced in size by heating the resist and causing it to flow. The results obtained with different mask dimensions and different wafer critical dimension (CD) targets are discussed. Results show that a process could be developed for printing 150 nm contact holes with 400 nm depth of focus at 5% exposure latitude. Finally, the through-pitch behavior as a function of reflow bake temperature is shown. Although the more isolated vias tend to show more shrinkage than the nested vias, it is shown that the deviation in size through pitch can be controlled by adjusting the mask dimension.

Image shortening and process development in BEOL lithography

The problem of image shortening is well known in semiconductor lithography. As rectangular features decrease in width, the length of the feature will print smaller than the mask image length. This problem places a constraint upon overall device design because space must be allowed for line extensions and/or adding to the side of features. Making corrections for image shortening requires mask redesign, which increases the time and cost of new product development.

Correlations between dissolution data and lithography of various resists

The fundamental basis of resist performance in semiconductor lithography is the creation of a dissolution gradient in the resist film. For positive resists the dissolution rate (DR) and dissolution characteristics of the exposed as well as unexposed regions are important factors in determining the performance of the resist. Since the establishment of the dissolution rate curve as a method for evaluating photographic materials, many investigators have tried to correlate dissolution rate data with lithographic performance in a systematic way.