Ronald R. Troutman

VLSI limitations from drain-induced barrier lowering

Drain-induced barrier lowering (DIBL) determines the ultimate proximity of surface diffusions and qualifies as one of the fundamental electrical limitations for VLSI. The important design parameters relating to DIBL are investigated using a numerical two-dimensional model, and a simple conceptual model is introduced as an aid for understanding the results. Under normal operating conditions of an IGFET, DIBL produces surface (rather than bulk) injection at the source. Comparison of a base case with a scaled design reveals that simple linear scaling by itself is insufficient for holding DIBL to a tolerable amount.

Subthreshold design considerations for insulated gate field-effect transistors

A knowledge of subthreshold behavior in an insulated gate field-effect transistor is important for circuits with low leakage specifications. This paper discusses the effect of drain voltage on the subthreshold region as the channel length becomes shorter, the effect of substrate bias on both the shift in and the slope of the subthreshold curves, and the effect of temperature on the subthreshold current characteristics. It is shown that all these effects can be incorporated into a simple one-dimensional model.

A transient analysis of latchup in bulk CMOS

This paper presents an analytical model of transient latchup in bulk CMOS that predicts the time-dependent current and voltage characteristics of the parasitic p-n-p-n structure. Not only does the model describe the conditions for transient latchup, but it also predicts a previously unreported phenomenon of dynamic recovery, which we have verified experimentally. Compact Stability criteria are presented for the p-n-p-n structure that delineate the roles of ramp rate and circuit parameters.

Technology directions for portable computers

This paper contains an evaluation of trends in the key system parameters (e.g., size, weight, function, performance, battery life) for battery-powered portable computers, together with a review of development trends in the technologies required for such systems. The discussion focuses on notebook-size portable computers. Those technologies which will have substantial impact on battery life and power budgets of future notebook computers receive the primary emphasis in this paper for example, liquid crystal displays, storage technology, wireless communication technology, and low power electronics. System power management is also be addressed. The basic theme of this paper is first to develop a view of what the key attributes of future notebook computers will be, and then to discuss how technologies must evolve to allow such systems to be advanced over the current state of the art in terms of portability and battery life. >

Simple model for threshold voltage in a short-channel IGFET

The threshold voltage of a short-channel IGFET can be expressed, in relation to that for a long-channel device, asV_{T} = V_{TLC} - \alpha - \betaV_{DS}. This behavior is deduced from a charge injection model and is verified both by two-dimensional numerical simulations and by actual threshold data.

Subthreshold characteristics of insulated-gate field-effect transistors

A simple analytical model is developed for the subthreshold region of insulated-gate field-effect transistors (IGFET). For short channels, it is necessary to extend the model to include two-dimensional band-bending effects at the source in order to describe correctly the reduction in threshold caused by high drain and substrate voltages. The model is experimentally verified over a wide range of bias conditions and channel lengths and is compared with one- and two-dimensional numerical models.

Ion-implanted threshold tailoring for insulated gate field-effect transistors

This paper develops a general threshold equation for long-channel insulated gate field-effect transistors which accounts for the effects of ion-implant profiles used in threshold tailoring. Although any integrable function used to describe the nonuniform doping will yield an analytical expression for threshold, a Gaussian function is chosen because it accurately describes the implanted profile following proper annealing, regardless of subsequent high-temperature steps during fabrication. Most profiles of interest are quasi-neutral, i.e., the spatial dependence of the majority carriers in the undepleted bulk is adequately described by the doping profile, but the threshold equation is shown to be an excellent approximation for non quasi-neutral profiles as well. Comparison with experimental results show the analytical expression to be in good agreement with data over a wide range of implant conditions and starting substrate resistivity.

Low-level avalanche multiplication in IGFET's

Results are presented for both theoretical and experimental analyses of low-level avalanche multiplication in an insulated gate field-effect transistor (IGFET). The theoretical model is derived from the ionization integral using a linear field approximation for the electric field at the drain. Experimental multiplication factors are determined by measuring channel and substrate currents. The model is shown to lead to reasonable agreement with data in the range of multiplication factors defined by (Mn- 1) less than unity.

Transmission line modeling of substrate resistances and CMOS latchup

Substrate resistance in epitaxial-CMOS is more appropriately viewed as a lossy transmission line than as a lumped resistor or as a resistance ladder network. Lossy transmission lines can be used to model a variety of substrate resistance configurations, including the resistance necessary to quantitatively predict turn on of the lateral parasitic bipolar during latchup. Voltage and current distributions predicted by the transmission line model are in excellent agreement with two-dimensional numerical simulations. Parameter values for the model are easily related to vertical doping profiles and to a wide variety of parasitic p-n-p-n layouts. For CMOS design the lateral bipolars bypass resistor, commonly found in lumped element models of the parasitic p-n-p-n, is replaced by a transfer resistance derived from the transmission line model. Butted substrate contacts are shown to provide a worst-case design situation.

Layout and bias considerations for preventing transiently triggered latchup in CMOS

This paper investigates several techniques for hardening CMOS curcuitry against transiently triggered latchup. Measurements of critical rise time are made on four variations of the p-n-p-n structure inherent to CMOS. For each structure the n-well and substrate shunt resistances are varied as is the substrate bias. These measurements are performed on both bulk and epi-samples using both topside and backside substrate contacts. Comparison of the parasitic bipolar transistors comprising the p-n-p-n structures reveals that differences in bipolar behavior do not completely explain the differences in p-n-p-n latchup behavior. Test results are used to rate the various hardening techniques.