Peter E. Cottrell

Hot-electron emission in N-channel IGFET's

This paper discusses the emission of both substrate and channel hot electrons from the silicon into the gate insulator of n-channel IGFETs. In each case the discussion begins with a physical model to elucidate the many parametric dependencies. The effect of changing important material and geometrical parameters as well as temperature and terminal voltages is documented with emission data. Under proper conditions the majority of emitted hot electrons are collected at the gate electrode, so that electron heating can be studied by directly observing gate current. In addition, gate current is a sensitive probe of trapping effects in the gate insulator, and it is shown how these measurements can be used to deduce long-term stability in IGFET structures.

Lateral ion implant straggle and mask proximity effect

Lateral scattering of retrograde well implants is shown to have an effect on the threshold voltage of nearby devices. The threshold voltage of both NMOSFETs and PMOSFETs increases in magnitude for conventional retrograde wells, but for triple-well isolated NMOSFETs the threshold voltage decreases for narrow devices near the edge of the well. Electrical data, SIMS, and SUPREM4 simulations are shown that elucidate the phenomenon.

Device and technology evolution for Si-based RF integrated circuits

The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for digital applications. Using the devices in the key circuit blocks for typical RF transceivers, we review and give trends for the FoMs that characterize active and passive RF devices. These FoMs include transit frequency at unity current gain f/sub T/, maximum frequency of oscillation f/sub MAX/ at unit power gain, noise, breakdown voltage, capacitor density, varactor and inductor quality, and the like. We use the specifications for wireless communications systems to show how different Si-based devices may achieve acceptable FoMs. We focus on Si complementary metal-oxide-semiconductor (CMOS), Si Bipolar CMOS, and Si bipolar devices, including SiGe heterojunction bipolar transistors, RF devices, and integrated circuits (ICs). We analyze trends in the FoMs for Si-based RF devices and ICs and show how these trends relate to the technology nodes of the 2003 International Technology Roadmap for Semiconductors. We also compare FoMs for the best reported performance of research devices and for the performance of devices manufactured in high volumes, typically more than 10 000 devices. Certain commercial equipment, instruments, or materials are identified in this article to specify adequately the experimental or theoretical procedures. Such identification does not imply recommendation by any of the host institutions of the authors, nor does it imply that the equipment or materials are necessarily the best available for the intended purpose.

SiGe heterojunction bipolar transistors and circuits toward terahertz communication applications

The relatively less exploited terahertz band possesses great potential for a variety of important applications, including communication applications that would benefit from the enormous bandwidth within the terahertz spectrum. This paper overviews an approach toward terahertz applications based on SiGe heterojunction bipolar transistor (HBT) technology, focusing on broad-band communication applications. The design, characteristics, and reliability of SiGe HBTs exhibiting record f/sub T/ of 375 GHz and associated f/sub max/ of 210 GHz are presented. The impact of device optimization on noise characteristics is described for both low-frequency and broad-band noise. Circuit implementations of SiGe technologies are demonstrated with selected circuit blocks for broad-band communication systems, including a 3.9-ps emitter coupled logic ring oscillator, a 100-GHz frequency divider, 40-GHz voltage-controlled oscillator, and a 70-Gb/s 4:1 multiplexer. With no visible limitation for further enhancement of device speed at hand, the march toward terahertz band with Si-based technology will continue for the foreseeable future.

Enchanced multi-threshold (MTCMOS) circuits using variable well bias

Advanced CMOS technology can enable high levels of performance with reduced active power at the expense of increased standby leakage, MTCMOS has previously been described as a method of reducing leakage in standby modes, by addition of a power supply interrupt switch. Enhancements using variable well bias and layout techniques are described and demonstrate increased performance and reduced leakage over conventional MTCMOS circuits.

Ultralow-power SRAM technology

An ultralow-standby-power technology has been developed in both 0.18-µm and 0.13-µm lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage six-transistor (6T) SRAM cell sizes are 4.81 µm2 and 2.34 µm2, corresponding respectively to the 0.18-µm and 0.13-µm design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25°C and is less than 400 fA per cell at 1.5 V, 85°C. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the well-known gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.

RFCMOS technology from 0.25/spl mu/m to 65nm: the state of the art

The effort to design RF circuits in CMOS is motivated by low cost and significant capacity for on-chip integration. We discuss some of the challenges of implementing RF designs in CMOS, focusing on those introduced by the changing properties of FETs as technology nodes scale and devices shrink. We present methods and tools, using which, designers can ease these challenges and reduce the risk of implementing RF circuits in CMOS.

Noise margin and leakage in ultra-low leakage SRAM cell design

Various aspects of ultra-low leakage static random-access memories (SRAM) cell design are considered. It is shown that the high threshold voltage relative to the power supply so improves the stability of the cell that the beta ratio of the design may be made very small for improved performance. Also, the ramifications of threshold uncertainty due to random dopant fluctuations are investigated, and it is shown that chip performance will be adversely affected by this phenomenon.

Multi-dimensional simulation of VLSI wiring capacitance

Accurate prediction of device current and the capacitance to be driven by that current is key to the design of FET logic and dynamic RAM circuits. This paper describes the application of two- and three-dimensional, finite-element simulation to estimate capacitance in VLSI structures. The measured total and coupling capacitances of narrow and closely-spaced lines agree with two-dimensional simulation results for an FET technology with a minimum feature size of 1.25 microns and two metal wiring levels. The capacitance of a second-metal line crossing a first-metal line is predicted with the three-dimensional model and found to be twice that estimated by two-dimensional models. Adjacent line coupling is shown to be a significant signal detractor in dynamic RAMs with closely-spaced, metal or diffused bit lines.

n-well design for trench DRAM arrays

The effects of n-well doping profile on the characteristics of SPT DRAM (substrate plate trench dynamic random access memory) data retention time are described and characterized. A retrograde n-well is shown to be desirable since it offers decreased well resistance without the modification of surface device characteristics. Retention time can be further improved with an n-well doping concentration that decreases monotically with increasing depth rather than a retrograde profile which has a doping peak below the silicon surface. An n-well with such a doping profile has superior median retention time and a reduced number of bits that fail a data retention test. This improvement has been demonstrated by the fabrication of 4-Mb SPT-cell DRAM arrays and test structures.<<ETX>>