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Dive into the research topics where Jerome B. Lasky is active.

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Featured researches published by Jerome B. Lasky.


IEEE Transactions on Electron Devices | 1991

Comparison of transformation to low-resistivity phase and agglomeration of TiSi/sub 2/ and CoSi/sub 2/

Jerome B. Lasky; James S. Nakos; Orison J. Cain; Peter J. Geiss

The phase transformation and stability of TiSi/sub 2/ on n/sup +/ diffusions are investigated. Narrower n/sup +/ diffusions require higher anneal temperatures, or longer anneal times, than wider diffusions for complete transitions from the high-resistivity C49 phase to the low-resistivity C54 phase. A model is presented which explains this in terms of the probability of forming C54 nuclei on narrow diffusions and the influence of diffusion width on C54 grain size. The results are that more C49 and C54 nucleation events are required to completely transform narrow lines. For thin TiSi/sub 2/ (40 nm), there is a narrow process window for achieving complete transformation without causing agglomeration of the TiSi/sub 2/. The process window decreases with decreasing silicide thickness. A significantly larger process window is achieved with short-time rapid annealing. Similar studies are performed for CoSi/sub 2/ on n/sup +/ and p/sup +/ diffusions. No linewidth dependence is observed for the transformation from CoSi/sub x/ to CoSi/sub 2/. There is a broad process window from 575 degrees C to 850 degrees C using furnace annealing, for which the low-resistivity phase is obtained without causing agglomeration. >


international electron devices meeting | 1991

A new three-dimensional MOSFET gate-induced drain leakage effect in narrow deep submicron devices

Stephen F. Geissler; B. Porth; Jerome B. Lasky; J. Johnson; Steven H. Voldman

A new MOSFET gate-induced drain leakage (GIDL) mechanism is observed in narrow-width trench-isolated MOSFET devices. Electrical measurements and device simulation show that this mechanism occurs due to electric-field enhancement at the three-dimensional intersection of the gate-to-drain overlap region and the trench corner. The enhanced electric field increases the GIDL current at the 3-D intersection region. This imposes another fundamental limit on MOSFET dielectric scaling in deep submicron narrow-width devices. Since the 3-D GIDL mechanism is caused by a high electric field, trench corner rounding and lightly doped drain junctions provide effective solutions.<<ETX>>


Archive | 2001

Fin field effect transistor with self-aligned gate

Jeffrey P. Gambino; Jerome B. Lasky; Jed H. Rankin


Archive | 2002

Double planar gated SOI MOSFET structure

James W. Adkisson; John A. Bracchitta; John J. Ellis-Monaghan; Jerome B. Lasky; Effendi Leobandung; Kirk D. Peterson; Jed H. Rankin


international electron devices meeting | 1985

Silicon-on-insulator (SOI) by bonding and ETCH-back

Jerome B. Lasky; S.R. Stiffler; F.R. White; J.R. Abernathey


Ibm Journal of Research and Development | 1995

The evolution of IBM CMOS DRAM technology

Eric Adler; John K. DeBrosse; Stephen F. Geissler; Steven J. Holmes; Mark D. Jaffe; Jeffrey B. Johnson; Charles W. Koburger; Jerome B. Lasky; Brian Lloyd; Glen L. Miles; James S. Nakos; Wendell P. Noble; Steven H. Voldman; Michael D. Armacost; Richard A. Ferguson


Archive | 1991

Semiconductor memory cell and memory array with inversion layer

Bruce A. Kauffmann; Chung Hon Lam; Jerome B. Lasky


Archive | 1987

Method of forming metal-strapped polysilicon gate electrode for FET device

John Robert Abernathey; John Edward Cronin; Jerome B. Lasky


Archive | 2002

Power distribution design method for stacked flip-chip packages

Jerome B. Lasky; Edward J. Nowak; Edmund J. Sprogis


Archive | 1994

Oxidation of silicon nitride in semiconductor devices

Stephen F. Geissler; Josef Warren Korejwa; Jerome B. Lasky; Pai-Hung Pan

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