Ruixue Ding

Electrical Modeling and Characterization of Shield Differential Through-Silicon Vias

An equivalent-circuit model of shield differential through-silicon vias (SDTSVs) in 3-D integrated circuits (3-D ICs) is proposed in this paper. The proposed model is verified using the 3-D full-wave field solver High Frequency Simulator Structure, showing that it is highly accurate up to 100 GHz. Furthermore, a full-wave extraction method for the resistance-inductance-capacitance-conductance (RLCG) parameters of SDTSVs is also proposed in this paper, which can be applied to all of differential transmission lines. It is shown that the results of the RLCG parameters obtained from the full-wave extraction method agree well with that from the analytical calculation up to 100 GHz, further validating the accuracy of the proposed model. Finally, using the proposed model, a deep analysis of electrical characteristics of SDTSVs is carried out to provide helpful design guidelines for them in future 3-D ICs.

Metal Proportion Optimization of Annular Through-Silicon via Considering Temperature and Keep-Out Zone

For annular through-silicon via (TSV)-based 3-D integrated circuits (3-D ICs), a greater TSV metal proportion of annular TSV leads to lower temperature but induces larger keep-out zone (KOZ). In this paper, the figure of merit (FOM) tradeoff model between temperature and KOZ is proposed to obtain the optimal metal proportion of annular TSV. First, the analytical models of the temperature of annular TSV-based 3-D IC and the KOZ induced by annular TSV are given, respectively, and both of them are verified by ANSYS software. Second, based on the analytical models, the FOM model is proposed. Then, the effects of total radius, material, and insertion density of annular TSV on FOM and optimal metal proportion are analyzed in detail. It is concluded that, the optimal metal proportion of annular TSV is approximately 0.3 with large ranges of the total radius and density of annular TSV, and various materials filled in annular TSV.

A Model of Air-Gap Through-Silicon Vias (TSVs) for Microwave Applications

In this letter, Ground-Signal-Ground type through-silicon vias (TSVs) are designed to achieve millimeter wave applications in three-dimensional integrated circuits (3-D ICs). Air-gap is exploited as the insulation layer due to the low permittivity. The accurate wideband equivalent-circuit model are established with frequency up to 20 GHz by using a set of resistance inductance capacitance conductance (RLGC) parameters, which are derived from the different design physical parameters and materials of the TSVs. Good agreements between the proposed models and full-wave simulation of Ansofts HFSS are shown over a wide frequency range of interest.

Parasitic Inductance of Non-Uniform Through-Silicon Vias (TSVs) for Microwave Applications

In this letter, the parasitic inductance of tapered ground-signal-ground (GSG) type through-silicon via (TSV) pair used in high speed three-dimensional integrated circuits (3-D ICs) are proposed. Rigorous closed-form formulas of the inductance, exploiting loop and partial inductances, are derived based on the geometric information with frequency up to 20 GHz, which also cover the cylinder and GS-mode TSVs. The proposed models are in good agreement with the 3-D electromagnetic (EM) simulator and measurement results with maximum errors of 8%.

Accurate Formulas for the Capacitance of Tapered-Through Silicon Vias in 3-D ICs

This letter first proposes novel formulas for the calculation of the oxide capacitance and the silicon substrate capacitance in Tapered-Through Silicon vias (T-TSVs). The electric field is non-uniform distribution in T-TSVs due to its non-uniform three-dimensional structure. In order to get accurate formulas for the capacitance of T-TSVs, the conformal mapping method was used properly based on the analytical results of the local electric field structure in T-TSVs. When the slope angle equals to zero, the obtained formulas can be reduced to the formulas of cylindrical TSVs. The comparison between the results of the proposed formulas and the three-dimensional quasi-static field solver shows that the proposed formulas have very high accuracy, with maximum errors of 1% and 3% for the oxide capacitance and the silicon substrate capacitance, respectively.

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We characterize quantitatively the noise-shielding effect of the p+ layer surrounding through-silicon via (TSV). In time domain, as for the rise time of input signal in picosecond scale, 1) the peak noise induced by TSV with p+ layer at the observe point (OP) is reduced by more than 91.8% compared with that of conventional TSV; 2) for the case without p+ layer, the threshold voltage and saturation current of nMOSFET are changed by as much as 80 mV and 120% due to the TSV-induced noise, respectively; while for the case with p+ layer, there are hardly any disturbance. In frequency domain, the transmission parameter from TSV to OP is decreased by 21~43 dB in the frequency range of 0.1 to 50 GHz, after the p+ layer is added. It is proved that the p+ layer can mitigate the TSV-induced substrate noise effectively for microwave applications.

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Accurate analytical models for the strain and stress in silicon induced by annular Through-silicon-via (TSV) are proposed. Finite element method (FEM) is used for the model verification. It is shown that errors for the strain and stress models are respectively less than 6.6% and 6.8% for various metal and dielectric materials. Based on the analytical model of stress, keep-out-zones (KOZs) are also evaluated for pMOS and nMOS, as the stress is parallel and perpendicular to transistor channel. Annular TSVs with various materials induce KOZs of less than 6.6μm. W exhibits the best thermo-mechanical performance with KOZ=0.

Layer in Mitigating Substrate Noise Induced by Through-Silicon Via for Microwave Applications

This paper presents an effective loop impedance extraction method and a model of a signal through-silicon via (TSV) surrounded by multiground TSVs. According to this method, the effective coupling substrate capacitances of multiground TSVs with different numbers and placements are calculated. Based on the calculated values of the resistance-inductance-capacitance-conductance (RLCG) parameters, the equivalent circuit and a two-port network model are established. The S-parameters of the model are validated by the simulated and measured results. Then, the effect of different patterns of ground TSVs on the central signal and coupling capacitance are discussed. Note that the hexagon pattern proposed in this paper can save the occupied area prominently without damaging the signal integrity.

Analytical models for the thermal strain and stress induced by annular through-silicon-via (TSV)

A new closed-form expression of 50% propagation delay for distributed RLC interconnects is proposed using the multivariable curve fitting method, with a maximum error of 4% with respect to SPICE results. Then accurate closed-form solutions for the optimum repeater number and size to minimize the propagation delay are further derived. The performance of single-walled carbon nanotube (SWCNT) bundle interconnects is evaluated using the proposed models in the intermediate and global levels at the 22- and 32-nm technology nodes, and compared against traditional Cu interconnects. It is shown that the performance of SWCNT bundle interconnects in propagation delay can outperform Cu interconnects, and the improvement will be enhanced with technology scaling and wire length increasing. On the other hand, the propagation delay of SWCNT bundle interconnects is super-linearly dependent on the wire length similar to Cu interconnects, indicating that the method of repeater insertion to reduce the propagation delay can also apply to SWCNT bundle interconnects. The results shown that repeater insertion can really reduce the propagation delay of SWCNT bundle interconnects effectively, and the optimum repeater number is much smaller than that of Cu interconnects.

Modeling and Optimization of Multiground TSVs for Signals Shield in 3-D ICs

An equivalent-circuit model of Cu-carbon nanotube heterogeneous coaxial through-silicon vias (HCTSVs) in 3-D integrated circuits (3-D ICs) is proposed in this paper. Based on the complex effective conductivity method, the resistances and inductances of Cu-single walled carbon nanotube (SWCNT) HCTSVs and Cu-multi walled carbon nanotube (MWCNT) HCTSVs are compared with that of Cu coaxial through-silicon vias (CTSVs). Furthermore, using the proposed model, the magnitudes of their insertion losses are compared. It is shown that the transmission performance of Cu-SWCNT HCTSVs with higher metallic fraction and Cu-MWCNT HCTSVs is better than that of Cu CTSVs, and the improvement of Cu-MWCNT HCTSVs is more obvious at high frequencies. Finally, the transmission characteristics of Cu-MWCNT HCTSVs are analyzed deeply to provide helpful design guidelines for them in future high-speed 3-D ICs.