Xiaoxian Liu

A Model of Air-Gap Through-Silicon Vias (TSVs) for Microwave Applications

In this letter, Ground-Signal-Ground type through-silicon vias (TSVs) are designed to achieve millimeter wave applications in three-dimensional integrated circuits (3-D ICs). Air-gap is exploited as the insulation layer due to the low permittivity. The accurate wideband equivalent-circuit model are established with frequency up to 20 GHz by using a set of resistance inductance capacitance conductance (RLGC) parameters, which are derived from the different design physical parameters and materials of the TSVs. Good agreements between the proposed models and full-wave simulation of Ansofts HFSS are shown over a wide frequency range of interest.

Parasitic Inductance of Non-Uniform Through-Silicon Vias (TSVs) for Microwave Applications

In this letter, the parasitic inductance of tapered ground-signal-ground (GSG) type through-silicon via (TSV) pair used in high speed three-dimensional integrated circuits (3-D ICs) are proposed. Rigorous closed-form formulas of the inductance, exploiting loop and partial inductances, are derived based on the geometric information with frequency up to 20 GHz, which also cover the cylinder and GS-mode TSVs. The proposed models are in good agreement with the 3-D electromagnetic (EM) simulator and measurement results with maximum errors of 8%.

Analytical models for the thermal strain and stress induced by annular through-silicon-via (TSV)

Accurate analytical models for the strain and stress in silicon induced by annular Through-silicon-via (TSV) are proposed. Finite element method (FEM) is used for the model verification. It is shown that errors for the strain and stress models are respectively less than 6.6% and 6.8% for various metal and dielectric materials. Based on the analytical model of stress, keep-out-zones (KOZs) are also evaluated for pMOS and nMOS, as the stress is parallel and perpendicular to transistor channel. Annular TSVs with various materials induce KOZs of less than 6.6μm. W exhibits the best thermo-mechanical performance with KOZ=0.

Modeling and Optimization of Multiground TSVs for Signals Shield in 3-D ICs

This paper presents an effective loop impedance extraction method and a model of a signal through-silicon via (TSV) surrounded by multiground TSVs. According to this method, the effective coupling substrate capacitances of multiground TSVs with different numbers and placements are calculated. Based on the calculated values of the resistance-inductance-capacitance-conductance (RLCG) parameters, the equivalent circuit and a two-port network model are established. The S-parameters of the model are validated by the simulated and measured results. Then, the effect of different patterns of ground TSVs on the central signal and coupling capacitance are discussed. Note that the hexagon pattern proposed in this paper can save the occupied area prominently without damaging the signal integrity.

Electrical Modeling and Analysis of Differential Dielectric-Cavity Through-Silicon via Array

The parasitic parameters and equivalent electrical model of differential dielectric-cavity through-silicon via (DDC-TSV) array on traditional low-resistivity silicon (LRSi) are proposed in this letter. TSV plugs are placed in the dielectric-cavity etched on LRSi. Each analytical formula in the model is established as the fuction of various physical geometries. The resistance–inductance–capacitance–conductance model and S-parameters of the DDC-TSV array are constructed by the Advanced Design System (ADS), which is verified by the 3-D full-wave electromagnetic solver High Frequency Simulator Structure (HFSS). Simulation results of the ADS and HFSS accord well with each other with frequencies up to 100 GHz, which shows good accuracy of the proposed model.

Closed-form expression for capacitance of tapered through-silicon-vias considering MOS effect

In this paper, closed-form expression of the parasitic capacitance of the tapered Through-Silicon Via (TSV) is proposed, which also cover the cylindrical TSV when the slop wall angle is 90°. The comparison between the results of Ansoft Q3D verification and Matlab calculation are made. It shows that the root mean square error is less than 6.10%, over a wide range of the bottom radius and the height of tapered TSV, and the oxide thickness, therefore, the expression presented proves to be accurate.

Reduction of signal reflection in high-frequency three-dimensional (3D) integration circuits

The through silicon via (TSV) technology provides a promising option to realize three dimensional (3D) gigscale systems with high performance. As the fundamental elements in this system, Redistribution Layers (RDLs), TSVs, and bumps, which constitute a TSV channel together, transmit high speed signals. Consequently the impedance mismatch among these elements causes signal reflection along the channel that need to be investigated. Chebyshev Multisection Matching Transformers are proposed to reduce the signal reflection of the TSV channel when operating frequency up to 20GHz, by utilizing of which S11 and S21 has been improved of 150% and 73.3%, respectively.

Parasitic effects of air-gap through-silicon vias in high-speed three-dimensional integrated circuits*

In this paper, ground-signal-ground type through-silicon vias (TSVs) exploiting air gaps as insulation layers are designed, analyzed and simulated for applications in millimeter wave. The compact wideband equivalent-circuit model and passive elements (RLGC) parameters based on the physical parameters are presented with the frequency up to 100 GHz. The parasitic capacitance of TSVs can be approximated as the dielectric capacitance of air gaps when the thickness of air gaps is greater than 0.75 μm. Therefore, the applied voltage of TSVs only needs to achieve the flatband voltage, and there is no need to indicate the threshold voltage. This is due to the small permittivity of air gaps. The proposed model shows good agreement with the simulation results of ADS and Ansofts HFSS over a wide frequency range.