S. Ben Dhia

Construction of an Integrated Circuit Emission Model of a FPGA

This paper describes the construction flow and the validation of an equivalent conducted emission model of a complex integrated circuit (a FPGA), based on the ICEM (Integrated Circuit Emission Model) modeling approach.

Development of an on-chip sensor for substrate coupling study in Smart Power mixed ICs

In order to merge low power and high voltage devices on the same chip at competitive cost, Smart Power integrated circuits (ICs) are extensively used. Electrical noise induced by power stage switching or external disturbances generates parasitic substrate currents, leading to a local shift of the substrate potential which can severely disturb low voltage circuits. Nowadays this is the major cause of failure of Smart Power ICs, inducing costly circuit redesign. Modern CAD tools cannot accurately simulate this injection of minority carriers in the substrate and their propagation in the substrate. In order to create a link between circuit design, modelling and implementation in innovative CAD tools there is a need to validate these models by measuring the high voltage perturbations that activate parasitic structures in the substrate directly on the chip. This paper presents an on-chip noise sensor dedicated to measurements of transient voltage fluctuations induced by high voltage activity and coupled by the substrate.

Predicting the risk of non-compliance to EMC requirements during the life-cycle

This paper presents a simulation flow for the prediction of the long-term evolution of EMC levels during the life-time of electronic devices or systems. This new requirement is essential to extend the warranty of critical applications operating in harsh environments. The simulation of the evolution of the electromagnetic emission of a switched-mode power supply is given as a validation case.

A review of research on the effect of aging on the EMC of integrated circuits

Electromagnetic compatibility (EMC) is an essential requirement to electronic systems in which integrated circuits have a major influence. Intrinsic degradation mechanisms, which produces anticipated wear-out in deep submicron components threat not only the reliability of circuits, but also EMC performances. The need to predict and ensure long-term EMC has become a key challenge. This paper aims at presenting the last results on the long-term EMC topic. The paper clarifies the effect of device degradation mechanisms on EMC level drifts during lifetime and presents some attempts to predict these evolutions.

Smart power mixed ICs parasitic bipolar coupling issues analysis with a dedicated on-chip sensor

The presence of low power and high voltage devices in Smart Power integrated circuits (ICs) cause parasitic substrate interaction between switched power stages and sensitive analog blocks. This in turn is the major cause of failure of Smart Power ICs, inducing costly circuit redesign. In order to predict these harmful events, there is a need in IC industry to create a link between circuit designs, modelling and implementation in innovative software tools. Thus there is a real need to validate these new SPICE models by measuring the high voltage perturbations that activate parasitic structures in the substrate directly on the chip. This paper presents an analysis of parasitic bipolar coupling issues in Smart Power Mixed ICs with a dedicated on-chip sensor. The possible scenarios based on PNP and NPN activation are derived and a real life test vehicle is introduced and investigated in detail. For verification purposes multiple of the developed on-chip sensors are placed close to the expected sensitive nodes. The architecture and the capabilities of the sensor like multiplexing, sensitivity and the calibration possibility are explained in detail. The on-chip sensor is used as an on-chip oscilloscope to measure the transient voltage fluctuations induced by high voltage activity and coupled by the substrate. The test vehicle was developed and produced in ams HV CMOS technology.