S. Cea

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.

A logic nanotechnology featuring strained-silicon

Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10 and 25%, respectively. The process flow consists of selective epitaxial Si/sub 1-x/Ge/sub x/ in the source/drain regions to create longitudinal uniaxial compressive strain in the p-type MOSFET. A tensile Si nitride-capping layer is used to introduce tensile uniaxial strain into the n-type MOSFET and enhance electron mobility. Unlike past strained-Si work: 1) the amount of strain for the n-type and p-type MOSFET can be controlled independently on the same wafer and 2) the hole mobility enhancement in this letter is present at large vertical electric fields, thus, making this flow useful for nanoscale transistors in advanced logic technologies.

Delaying forever: Uniaxial strained silicon transistors in a 90nm CMOS technology

We describe the device physics of uniaxial strained silicon transistors. Uniaxial strain is more effective, less costly and easier to implement. The highest PMOS drive current to date is reported: 0.72mA/ /spl mu/m. Pattern sensitivity and mobility/Rext partitioning are discussed. Finally we measure inverter delays as low as 4.6pS, and show 50Mb SRAMs operational at 0.65V.

Bandgap engineering of group IV materials for complementary n and p tunneling field effect transistors

Direct bandgap transition engineering using stress, alloying, and quantum confinement is proposed to achieve high performing complementary n and p tunneling field effect transistors (TFETs) based on group IV materials. The critical tensile stress for this transition decreases in Ge1−xSnx for Sn content 0≤x≤0.068, calculated with the Nonlocal Empirical Pseudopotential method. Direct sub eV bandgap leads to high ON current in both n and p Ge and Ge1−xSnx TFETs, simulated using the sp3d5s*-SO model. Ge and Ge1−xSnx show an advantage over III-V p TFETs achieving steep subthreshold operation, which is limited in III-V devices by their low density of electron states.

High performance Hi-K + metal gate strain enhanced transistors on (110) silicon

For the first time, the performance impact of (110) silicon substrates on high-k + metal gate strained 45 nm node NMOS and PMOS devices is presented. Record PMOS drive currents of 1.2 mA/um at 1.0 V and 100 nA/um Ioff are reported. It will be demonstrated that 2D short channel effects strongly mitigate the negative impact of (110) substrates on NMOS performance. Narrow width (110) device performance is shown and compared to (100) for the first time. Device reliability is also reported showing no fundamental issue for (110) substrates.

Quantum mechanical calculation of hole mobility in silicon inversion layers under arbitrary stress

We have developed a quantum anisotropic transport model for holes which, for the first time, allows mobility to be studied under both uniaxial and arbitrary stress in PMOS inversion layers. The anisotropic bandstructure of a 2D quantum gas is computed from a 6-band stress dependent k.p Hamiltonian. Our unique momentum-dependent scattering model also captures the anisotropy of scattering. A comprehensive study has been performed for uniaxial stress, biaxial stress, and their nonlinear interactions. The results are compared with device bending data and piezoresistance data, showing very good agreement.

Drive current enhancement in p-type metal–oxide–semiconductor field-effect transistors under shear uniaxial stress

Recent attention has been given to metal–oxide–semiconductor field-effect transistor (MOSFET) device designs that utilize stress to achieve performance gain in both n-type MOSFETs (NMOS) and p-type MOSFETs (PMOS). The physics behind NMOS gain is better understood than that of PMOS gain, which has received less attention. In this letter, we describe the warping phenomena which is responsible for the gain seen in [110] uniaxially stressed PMOS devices on [100] orientated wafers. We also demonstrate that shear uniaxial stress in PMOS is better suited to MOSFET applications than biaxial stress as it is able to maintain gain at high vertical and lateral fields.

Front end stress modeling for advanced logic technologies

This paper presents an integrated approach to modeling front end stress which has been used to investigate the main sources of stress in advanced logic technologies and how they can be used to improve device performance. The approach is illustrated with the evaluation of several technologically important stress options.

Understanding stress enhanced performance in Intel 90nm CMOS technology

A hierarchical, model-based understanding of the key physical effects underlying stress-induced device performance gain is presented, focusing on the large gains seen for uniaxial PMOS stress conditions and the vertical stress impact on NMOS gain.

Comparison of Discretization Methods for Device Simulation

The characteristics of semiconductor devices are modeled by three coupled nonlinear partial differential equations consisting of the electron continuity, hole continuity, and Poisson equations. A variety of discretization approaches can be used to solve these equations. This paper compares finite volume Scharfetter-Gummel and finite element quasi-Fermi discretization schemes for a variety of devices and mesh element types. The simulation results show that a quasi-Fermi approach may be preferable to the more common finite volume Scharfetter-Gummel method for certain device simulation applications. Keywords-device simulation; discretization methods; finite volume method; finite element method; single-event upset