Mark Stettler

Analysis of graphene nanoribbons as a channel material for field-effect transistors

Electronic properties of graphene (carbon) nanoribbons are studied and compared to those of carbon nanotubes. The nanoribbons are found to have qualitatively similar electron band structure which depends on chirality but with a significantly narrower band gap. The low- and high-field mobilities of the nanoribbons are evaluated and found to be higher than those of carbon nanotubes for the same unit cell but lower at matched band gap or carrier concentration. Due to the inverse relationship between mobility and band gap, it is concluded that graphene nanoribbons operated as field-effect transistors must have band gaps <0.5eV to achieve mobilities significantly higher than those of silicon and thus may be better suited for low power applications.

Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors

Summary form only given. We investigate scaling challenges and outline device design requirements needed to support high performance-low power planar CMOS transistor structures with physical gate lengths (L/sub GATE/) below 50 nm. This work uses a combination of simulation results, experimental data and critical analysis of published data. A realistic assessment of gate oxide thickness scaling and maximum tolerable oxide leakage is provided. We conclude that the commonly accepted upper limit of 1 A/cm/sup 2/ for gate leakage is overly pessimistic and that leakage values of up to 100 A/cm/sup 2/ are deemed acceptable for future logic technology generations. Unique channel mobility and junction edge leakage degradation mechanisms, which become prominent at 50 nm L/sub GATE/ dimensions, are highlighted using quantitative analysis. Source-drain extension (SDE) profile design requirements to simultaneously minimize short channel effects (SCE) and achieve low parasitic resistance for sub-50 nm L/sub GATE/ transistors are described for the first time.

Assessment of room-temperature phonon-limited mobility in gated silicon nanowires

The technologically important question of whether the reduced density of electron states (DOS) for scattering in one-dimensional (1D) wire transport devices gives an advantage over the planar metal–oxide–semiconductor field-effect-transistor (MOSFET) for electron mobility is assessed by simulations. We self-consistently solve the Schrodinger–Poisson equations to calculate phonon-limited electron mobility in a multisubband cylindrical Si gated wire. We find that the benefit of reduced 1D DOS is offset by an increased phonon scattering rate due to increased electron–phonon wave function overlap and results in a degraded mobility in narrow wires. The applied gate bias voltage and the wire size control the transition from wire geometry to surface field-dominated confinement. The size scale for this 1D to two-dimensional (2D) transition is also found to be surprisingly small: A wire with a 75 A radius has an essentially 2D DOS and has a 2D mobility that is degraded from the planar (100) MOSFET due to the aniso...

Source/drain extension scaling for 0.1 /spl mu/m and below channel length MOSFETs

In this paper, we investigate the scaling of source/drain extension (SDE) depth and SDE to gate overlap for 0.1 /spl mu/m and below MOSFETs. We show for the first time that a minimum SDE to gate overlap of 15-20 nm is needed to prevent drive current (I/sub DSAT/) degradation. We also show for the first time that scaling SDE vertical depths below 30-40 nm results in little to no performance benefit for 0.1 /spl mu/m devices and beyond since any improvement in short channel effects due to reduced charge sharing is offset by a large increase in external resistance and poor gate coupling between the channel and extensions.

Quantum mechanical calculation of hole mobility in silicon inversion layers under arbitrary stress

We have developed a quantum anisotropic transport model for holes which, for the first time, allows mobility to be studied under both uniaxial and arbitrary stress in PMOS inversion layers. The anisotropic bandstructure of a 2D quantum gas is computed from a 6-band stress dependent k.p Hamiltonian. Our unique momentum-dependent scattering model also captures the anisotropy of scattering. A comprehensive study has been performed for uniaxial stress, biaxial stress, and their nonlinear interactions. The results are compared with device bending data and piezoresistance data, showing very good agreement.

Drive current enhancement in p-type metal–oxide–semiconductor field-effect transistors under shear uniaxial stress

Recent attention has been given to metal–oxide–semiconductor field-effect transistor (MOSFET) device designs that utilize stress to achieve performance gain in both n-type MOSFETs (NMOS) and p-type MOSFETs (PMOS). The physics behind NMOS gain is better understood than that of PMOS gain, which has received less attention. In this letter, we describe the warping phenomena which is responsible for the gain seen in [110] uniaxially stressed PMOS devices on [100] orientated wafers. We also demonstrate that shear uniaxial stress in PMOS is better suited to MOSFET applications than biaxial stress as it is able to maintain gain at high vertical and lateral fields.

Front end stress modeling for advanced logic technologies

This paper presents an integrated approach to modeling front end stress which has been used to investigate the main sources of stress in advanced logic technologies and how they can be used to improve device performance. The approach is illustrated with the evaluation of several technologically important stress options.

Inversion mobility and gate leakage in high-k/metal gate MOSFETs

For the first time, we show with simulation that the use of a metal gate/high-k stack offers improved mobility over polysilicon/high-k gates stacks while maintaining decreased gate leakage compared to conventional SiO/sub 2/ stacks, thus allowing high-performance transistor scaling to continue.

Understanding stress enhanced performance in Intel 90nm CMOS technology

A hierarchical, model-based understanding of the key physical effects underlying stress-induced device performance gain is presented, focusing on the large gains seen for uniaxial PMOS stress conditions and the vertical stress impact on NMOS gain.

A microscopic study of transport in thin base silicon bipolar transistors

A comprehensive study of electron transport within silicon bipolar transistors with varying base widths is conducted using a rigorous microscopic model, the scattering matrix approach. Results are presented for the base transit time, current, and the velocity and concentration profiles as a function of basewidth. Unlike previous analyses which artificially impose boundary conditions for the distribution function at the edges of the base, this study rigorously treats transport through both the emitter and collector space charge regions. The results are then compared with other transport models and reveal that even for very thin bases a properly modified drift-diffusion expression gives surprisingly good agreement with the rigorous model for the transit time and current. Finally, an analysis of the distribution function at the collector edge of the base shows that the electron velocity can exceed the thermal velocity (2k/sub B/T//spl pi/m*) in a zero-field region, contrary to the assumptions of several authors. >