Roza Kotlyar

Analysis of graphene nanoribbons as a channel material for field-effect transistors

Electronic properties of graphene (carbon) nanoribbons are studied and compared to those of carbon nanotubes. The nanoribbons are found to have qualitatively similar electron band structure which depends on chirality but with a significantly narrower band gap. The low- and high-field mobilities of the nanoribbons are evaluated and found to be higher than those of carbon nanotubes for the same unit cell but lower at matched band gap or carrier concentration. Due to the inverse relationship between mobility and band gap, it is concluded that graphene nanoribbons operated as field-effect transistors must have band gaps <0.5eV to achieve mobilities significantly higher than those of silicon and thus may be better suited for low power applications.

Process Technology Variation

Moores law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moores law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing

This work demonstrates the steepest subthreshold swing (SS &#60; 60mV/decade) ever reported in a III–V Tunneling Field Effect Transistor (TFET) by using thin gate oxide, heterojunction engineering and high source doping. Owing to a lower source-to-channel tunnel barrier height, heterojunction III–V TFETs demonstrate steeper subthreshold swing (SS) at a given drain current (ID) and improved drive current compared to the homojunction III–V TFETs. Electrical oxide thickness (EOT) scaling and increased source doping in tandem with tunnel barrier height reduction are shown to greatly improve the SS of the III–V TFETs and increase ID by more than 20X.

Assessment of room-temperature phonon-limited mobility in gated silicon nanowires

The technologically important question of whether the reduced density of electron states (DOS) for scattering in one-dimensional (1D) wire transport devices gives an advantage over the planar metal–oxide–semiconductor field-effect-transistor (MOSFET) for electron mobility is assessed by simulations. We self-consistently solve the Schrodinger–Poisson equations to calculate phonon-limited electron mobility in a multisubband cylindrical Si gated wire. We find that the benefit of reduced 1D DOS is offset by an increased phonon scattering rate due to increased electron–phonon wave function overlap and results in a degraded mobility in narrow wires. The applied gate bias voltage and the wire size control the transition from wire geometry to surface field-dominated confinement. The size scale for this 1D to two-dimensional (2D) transition is also found to be surprisingly small: A wire with a 75 A radius has an essentially 2D DOS and has a 2D mobility that is degraded from the planar (100) MOSFET due to the aniso...

Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications

In this work, non-planar, multi-gate InGaAs quantum well field effect transistors (QWFETs) with high-K gate dielectric and ultra-scaled gate-to-drain and gate-to-source separations (LSIDE) of 5nm are reported for the first time. The high-K gate dielectric formed on this non-planar device structure has the expected thin TOXE of 20.5Å with low JG, and high quality gate dielectric interface. The simplified S/D scheme is needed for the non-planar architecture while achieving significant reduction in parasitic resistance. Compared to the planar high-K InGaAs QWFET with similar TOXE, the non-planar, multi-gate InGaAs QWFET shows significantly improved electrostatics due to better gate control. The results of this work show that non-planar, multi-gate device architecture is an effective way to improve the scalability of III–V QWFETs for low power logic applications.

High mobility Si/SiGe strained channel MOS transistors with HfO/sub 2//TiN gate stack

We integrate a strained Si channel with HfO/sub 2/ dielectric and TiN metal gate electrode to demonstrate NMOS transistors with electron mobility better than the universal mobility curve for SiO/sub 2/, inversion equivalent oxide thickness of 1.4 nm (EOT=1 nm), and with three orders of magnitude reduction in gate leakage. To understand the physical mechanism that improves the inversion electron mobility at the HfO/sub 2//strained Si interface, we measure mobility at various temperatures and extract the various scattering components.

Bandgap engineering of group IV materials for complementary n and p tunneling field effect transistors

Direct bandgap transition engineering using stress, alloying, and quantum confinement is proposed to achieve high performing complementary n and p tunneling field effect transistors (TFETs) based on group IV materials. The critical tensile stress for this transition decreases in Ge1−xSnx for Sn content 0≤x≤0.068, calculated with the Nonlocal Empirical Pseudopotential method. Direct sub eV bandgap leads to high ON current in both n and p Ge and Ge1−xSnx TFETs, simulated using the sp3d5s*-SO model. Ge and Ge1−xSnx show an advantage over III-V p TFETs achieving steep subthreshold operation, which is limited in III-V devices by their low density of electron states.

The ultimate CMOS device and beyond

For the past 40 years, relentless focus on Moores Law transistor scaling has delivered ever-improving CMOS transistor density. This paper discusses architectural and materials options which will contribute to the ultimate CMOS device. In addition, the paper reviews device options beyond the ultimate CMOS device.

High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III–V CMOS architecture

In this article we demonstrate a Ge p-channel QWFET with scaled TOXE = 14.5Å and mobility of 770 cm2/V*s at ns =5×1012 cm−2 (charge density in the state-of-the-art Si transistor channel at Vcc = 0.5V). For thin TOXE &#60; 40 Å, this represents the highest hole mobility reported for any Ge device and is 4× higher than state-of-the-art strained silicon. The QWFET architecture achieves high mobility by incorporating biaxial strain and eliminating dopant impurity scattering. The thin TOXE was achieved using a Si cap and a low Dt transistor process, which has a low oxide interface Dit. Parallel conduction in the SiGe buffer was suppressed using a phosphorus junction layer, allowing healthy subthreshold slope in Ge QWFET for the first time. The Ge QWFET achieves an intrinsic Gmsat which is 2× higher than the InSb p-channel QWFET [3]. These results suggest the Ge QWFET is a viable p-channel option for non-silicon CMOS.

High performance Hi-K + metal gate strain enhanced transistors on (110) silicon

For the first time, the performance impact of (110) silicon substrates on high-k + metal gate strained 45 nm node NMOS and PMOS devices is presented. Record PMOS drive currents of 1.2 mA/um at 1.0 V and 100 nA/um Ioff are reported. It will be demonstrated that 2D short channel effects strongly mitigate the negative impact of (110) substrates on NMOS performance. Narrow width (110) device performance is shown and compared to (100) for the first time. Device reliability is also reported showing no fundamental issue for (110) substrates.