S.H. Gu

Data retention behavior of a SONOS type two-bit storage flash memory cell

Data retention loss mechanisms in a 2-bit SONOS type flash EEPROM cell with hot electron programming and hot hole erase are investigated. In erase (low-Vt) state, a threshold voltage drift with storage time is observed after P/E cycling stress. Positive trapped charge creation in the bottom oxide is found to be responsible for the drift. In program (high-Vt) state, data retention loss is attributed mostly to nitride charge escape by Frenkel-Poole emission and oxide trap assisted tunneling. A square-root dependence of the nitride charge loss on electric field is obtained. A Vg-acceleration method for retention lifetime measurement is proposed.

Cause of data retention loss in a nitride-based localized trapping storage flash memory cell

Data retention loss in a localized trapping storage flash memory cell with a SONOS type structure is investigated. Both charge loss through the bottom oxide and lateral migration of trapped charges in the nitride layer are considered for the data retention loss. Charge pumping and charge separation methods are used in this study. Our results reveal that in normal operation condition the retention loss is mainly caused by charge leakage via P/E stress created oxide traps.

Numerical Simulation of Bottom Oxide Thickness Effect on Charge Retention in SONOS Flash Memory Cells

In this paper, bottom-oxide thickness (Tbo) and program/erase stress effects on charge retention in SONOS Flash memory cells with FN programming are investigated. Utilizing a numerical analysis based on a multiple electron-trapping model to solve the Shockley-Read-Hall rate equations in nitride, we simulate the electron-retention behavior in a SONOS cell with Tbo from 1.8 to 5.0 nm. In our model, the nitride traps have a continuous energy distribution. A series of Frenkel-Poole (FP) excitation of trapped electrons to the conduction band and electron recapture into nitride traps feature the transitions between the conduction band and trap states. Conduction band electron tunneling via oxide traps created by high-voltage stress and trapped electron direct tunneling through the bottom oxide are included to describe various charge leakage paths. We measure the nitride-charge leakage current directly in a large-area device for comparison. This paper reveals that the charge-retention loss in a high-voltage stressed cell, with a thicker bottom oxide (5 nm), exhibits two stages. The charge-leakage current is limited by oxide trap-assisted tunneling in the first stage and, then, follows a 1/t time dependence due to the FP emission in the second stage. The transition time from the first stage to the second stage is related to oxide trap-assisted tunneling time but is prolonged by a factor

Reliability models of data retention and read-disturb in 2-bit nitride storage flash memory cells

The reliability issues of two-bit storage nitride flash memory cells, including low-V/sub t/ state threshold voltage instability, read-disturb, and high-V/sub t/ state charge loss are addressed. The responsible mechanisms and reliability models are discussed. Our study shows that the cell reliability is strongly dependent on operation methods and process conditions.

Extraction of nitride trap density from stress induced leakage current in silicon-oxide-nitride-oxide-silicon flash memory

The authors propose a technique to extract a silicon nitride trap density from stress induced leakage current in a polycrystalline silicon-oxide-nitride-oxide-silicon flash memory cell. An analytical model based on the Frenkel-Poole emission is developed to correlate a nitride trap density with stress induced leakage current. The extracted nitride trap density is 7.0×1012cm−2eV−1. They find that nitride trapped charges have a rather uniform distribution in an energy range of measurement (∼0.2eV).

Read Current Instability Arising from Random Telegraph Noise in Localized Storage, Multi-Level SONOS Flash Memory

Program/erase cycling stress induced read current fluctuations arising from random telegraph noise (RTN) in a localized storage, multi-level nitride flash memory (SONOS) is explored. Our study shows that localized charge storage significantly enhances RTN. The amplitude of RTN varies in different program levels of a multi-level cell. The broadening of read current distribution due to RTN is characterized and modeled. Improvement of bottom oxide robustness can reduce the read current fluctuations

Characterization of programmed charge lateral distribution in a two-bit storage nitride flash memory cell by using a charge-pumping technique

In this paper, we use a modified charge pumping technique to characterize the programmed charge lateral distribution in a hot electron program/hot hole erase, two-bit storage nitride Flash memory cell. The stored charge distribution of each bit over the source/drain junctions can be profiled separately. Our result shows that the second programmed bit has a broader stored charge distribution than the first programmed bit. The reason is that a large channel field exists under the first programmed bit during the second bit programming. Such a large field accelerates channel electrons and causes earlier electron injection into the nitride. In addition, we find that programmed charges spread further into the channel as program/erase cycle number increases.

Characterization and Monte Carlo Analysis of Secondary Electrons Induced Program Disturb in a Buried Diffusion Bit-line SONOS Flash Memory

A new program disturb in a buried diffusion bit-line SONOS array is observed as a bit-line width is reduced. A multi-step Monte Carlo simulation is performed to explore the disturb mechanism. We find that the Vt shift of a disturbed cell is attributed to impact ionization-generated secondary electrons in a neighboring cell when it is in programming. The effects of substrate bias, bit-line dimension and pocket implant on the program disturb are characterized and evaluated by a Monte Carlo simulation.

Investigation of programmed charge lateral spread in a two-bit storage nitride flash memory cell by using a charge pumping technique

The lateral distribution of programmed charge in a hot electron program/hot hole erase nitride storage flash cell is investigated by using a charge pumping technique. Our study shows that the secondly programmed bit has a wider trapped charge distribution than the first programmed bit. In addition, we find programmed charge spreads further into the channel with program/erase cycle number.

Soft breakdown enhanced hysteresis effects in ultra-thin oxide SOI nMOSFETs

The impact of soft breakdown location on V/sub t/ hysteresis in partially depleted SOI nMOSFETs with ultra-thin oxide (1.6 nm) is investigated. Two breakdown enhanced hysteresis modes are identified. In a channel breakdown MOSFET, excess holes attributed to valence electron tunneling flow to the floating body and thus cause V/sub t/ hysteresis in gate bias switching. In contrast, for a drain-edge breakdown device, enhanced V/sub t/ hysteresis is observed during drain bias switching because of increased band-to-band tunneling current.