T.C. Lu

PHINES: a novel low power program/erase, small pitch, 2-bit per cell flash memory

A novel flash memory cell named PHINES (Programming by hot Hole Injection Nitride Electron Storage) is proposed. PHINES uses a nitride trapping storage cell structure, and channel FN erase is performed to raise Vt while programming is done by lowering local Vt through band-to-band hot hole injection. Two physical bits storage, low power P/E, high endurance, good retention and high scaling capability are achieved.

Reliability models of data retention and read-disturb in 2-bit nitride storage flash memory cells

The reliability issues of two-bit storage nitride flash memory cells, including low-V/sub t/ state threshold voltage instability, read-disturb, and high-V/sub t/ state charge loss are addressed. The responsible mechanisms and reliability models are discussed. Our study shows that the cell reliability is strongly dependent on operation methods and process conditions.

Novel operation schemes to improve device reliability in a localized trapping storage SONOS-type flash memory

Over erasure, charge gain in the low Vt state, and charge loss in the high Vt state are found to be the most severe reliability issues in a localized trapping storage flash memory cell. In this paper, based on our understanding of physical mechanisms, we demonstrate that by adding vertical electrical field treatments during program/erase operations, the over erasure and data retentivities in high/low Vt states are significantly improved.

Lateral migration of trapped holes in a nitride storage flash memory cell and its qualification methodology

The negative threshold voltage (V/sub t/) shift of a nitride storage flash memory cell in the erase state will result in an increase in leakage current. By utilizing a charge pumping method, we found that trapped hole lateral migration is responsible for this V/sub t/ shift. Hole transport in nitride is characterized by monitoring gate induced drain leakage current and using a thermionic emission model. The hole emission induced V/sub t/ shift shows a linear correlation with bake time in a semi-logarithm plot and its slope depends on the bake temperature. Based on the result, an accelerated qualification method for the negative V/sub t/ drift is proposed.

A novel NAND-type PHINES nitride trapping storage flash memory cell with physically 2-bits-per-cell storage, and a high programming throughput for mass storage applications

A novel NAND-type PHINES nitride trapping storage flash memory cell is proposed for the first time. PHINES memory cells use a SONOS cell structure, and are arranged in a modified NAND array. FN electron injection and band-to-band (BTB) hot-hole (HH) injection are utilized as the erase and the program operations, respectively. Read is performed by a novel BTB current sensing scheme. Physically 2-bits-per-cell storage, low power operation, and a high programming throughput are demonstrated.

Characterization and Monte Carlo Analysis of Secondary Electrons Induced Program Disturb in a Buried Diffusion Bit-line SONOS Flash Memory

A new program disturb in a buried diffusion bit-line SONOS array is observed as a bit-line width is reduced. A multi-step Monte Carlo simulation is performed to explore the disturb mechanism. We find that the Vt shift of a disturbed cell is attributed to impact ionization-generated secondary electrons in a neighboring cell when it is in programming. The effects of substrate bias, bit-line dimension and pocket implant on the program disturb are characterized and evaluated by a Monte Carlo simulation.

Reliability and device scaling challenges of trapping charge flash memories

As flash memories move toward the giga-bits era, several challenges limit their scalability. Floating gate flash memories face the problems of un-scalable tunnel oxide, and the last technology node of NOR flash was predicted to be 65 nm, based on the extrapolation of the difference between physical and electrical cell dimensions vs. generations, which drops to zero at 45 nm. Although SONOS-type flash memories show better scalability and simpler process, there are still some difficulties. In this paper, three SONOS-type flash memories (SONOS, NROM and PHINES) are compared and the scaling problems and reliability issues are disclosed.

Investigation of programmed charge lateral spread in a two-bit storage nitride flash memory cell by using a charge pumping technique

The lateral distribution of programmed charge in a hot electron program/hot hole erase nitride storage flash cell is investigated by using a charge pumping technique. Our study shows that the secondly programmed bit has a wider trapped charge distribution than the first programmed bit. In addition, we find programmed charge spreads further into the channel with program/erase cycle number.

A novel fully CMOS process compatible PREM for SOC applications

A novel nonvolatile memory cell named programmable resistor with eraseless memory (PREM) is proposed for system on chip applications for the first time. PREM combines a novel eraseless algorithm and the progressive breakdown of an ultrathin oxide. No or one extra mask is needed with a standard CMOS process. Multitime programming, multilevel cell, nonvolatility, and low-voltage operation are realized. Good reliability is demonstrated based on the result of a single cell.

A novel silicon-nitride based light-emitting transistor (SiNLET): optical/electrical properties of a SONOS-type three-terminal electroluminescence device for optical communication in ULSI

A novel silicon-nitride based light-emitting transistor (SiNLET) is proposed for the first time. This three-terminal electroluminescence device uses a SONOS-type device structure, and its process is compatible to standard CMOS devices. Photons are generated by Fowler-Nordheim electron (FN-E) tunnel-injection, band-to-band tunneling induced hot-hole (BTBT-HH) injection, and carrier scattering/trapping/recombination via nitride traps. SiNLET with an effective device area of 0.616 mum2 is demonstrated for display and optical communication purposes