S. Hanamura

Performance and hot-carrier effects of small CRYO-CMOS devices

The performance characteristics of submicrometer CMOS devices operating at low/cryogenic temperatures (CRYO-CMOS) are determined. The advantages and problems in a CRYO-CMOS technology are experimentally studied in relation to the velocity saturation, source-drain resistances, mobility behavior, carrier freeze-out effects, hot-carrier effects, and circuit performance. The increase of the maximum transconductance at low temperatures (77, 4.2 K) has been confirmed even in the submicrometer channel region. However, improvement of inabilities at a VGnearly equal to 5 V is not so significant in devices with thinner oxides and less so in pMOS devices than in nMOS devices. Excellent subthreshold characteristics have been obtained at low temperatures, making very low-voltage operation possible. One problem found in the threshold control of pMOS transistors is that the boron ions implanted in the surface freeze out, causing unusual subthreshold behavior. Circuit delays have been improved by a factor of 2 to 3, and CRYO-CMOS shows the lowest power-delay product among existing semiconductor technologies with speed performance comparable to bipolar ECL devices. For LDD devices, speed improvements are only slightly smaller than for single-drain devices, while currents and transconductances in the linear regions are limited because of carrier freeze-out of the lightly doped drain. For both channel LDD devices, the transconductance degradations and VTshifts observed under dc stress conditions at 77 K are considered to result from electron injection into spacer oxides.

MOS area sensor: Part II—Low-noise MOS area sensor with antiblooming photodiodes

The development of a high-sensitivity 320 × 244 element MOS area sensor and a novel fixed pattern noise (FPN) suppressing circuit are reported in this paper. The new device incorporates p+-n+high-C photodiodes and double-diffused sense lines. The p+-n+high-Cphotodiodes provide a large dynamic range and a large saturation signal of 1.4 µA with 6-1x W-lamp illumination. The double-diffused sense lines are introduced to vastly improve blooming characteristics, making use of a built-in potential barrier. FPN is proved to stem mainly from inversion charge variations through horizontal switching MOS gate capacitances. A simple high-performance FPN suppressing circuit is proposed which realizes high signal-to-noise (S/N) ratios of more than 68 dB at saturation. The new sensor is tested in a high-sensitivity black-and-white VTR hand-held camera and will find broad applications.

MOS area sensor: Part I—Design consideration and performance of an n-p-n structure 484 × 384 element color MOS imager

The design consideration and performance of an n-p-n structure 484 × 384 element MOS imager is described. The imager has a photodiode array and scanners separately integrated on different p wells. The horizontal scanner, consisting of bootstrapping type noninverting circuits, features high speed and low noise. The maximum scan rate of the scanner is ∼15 MHz. The vertical scanner, consisting of inverting circuits, has a wide dynamic operating range. It can operate stably under an intense illumination of ∼ 1500 1x. Analysis of the MOS switch with a photodiode is also carried out. The 484 × 384 imager has shown excellent performances: signal to fixed-pattern-noise ratio of 54 dB, horizontal resolution of 260 TV lines, vertical resolution of 350 TV lines, well-balanced spectral response, and antiblooming.

Low-temperature CMOS 8 × 8 bit multipliers with sub-10-ns speeds

Low-temperature (77, 4.2 K) operation is proposed for bulk CMOS devices for use in super-fast VLSI applications. Symmetrical variations of both types of MOSFET parameters with respect to temperature and latchup immunity make CMOS a very promising device technology at low temperatures. To demonstrate the performance advantage of circuit operation at low temperatures, multipliers with two different circuit configurations are designed and fabricated with a gate length of 1.3 µm. Multiplication speeds of 8.0 and 6.6 ns are obtained with CMOS circuit configurations at 4.2 K and with pulsed-p-load/CMOS circuit configurations at 77 K, respectively.

A 9 ns 1 Mb CMOS SRAM

A 1-Mb (256k*4/1M*1) CMOS SRAM (static random access memory), fabricated using a half-micron triple-poly double-metal CMOS technology, is reported. A 9-ns access time is attained with 5-V supply and 30-pF load capacitance. This access time has been achieved with a three-stage pMOS cross-coupled sense amplifier, 0.6- mu m high-performance MOSFETs, and an optimized internal supply voltage scheme. A redundancy scheme with no access time penalty has been incorporated. The sense amplifier circuit combined with a CMOS cross-coupled preamplifier has under 10-ns access time. Address and data output waveforms are shown. Typical active current is 55 mA at 30 MHz, and typical standby current is 15 mA (TTL). Typical RAM characteristics are listed.<<ETX>>

A 256K CMOS SRAM with internal refresh

A four-transistor switched-capacitor load SRAM employing 0.8μm CMOS technology with a cell size of 39.2μm2will be reported. The approach makes it possible to access without time-loss for internal refresh. Access time is 43ns and standby power is 3.3μW.

Low temperature CMOS 8 &#215; 8b multipliers with sub 10ns speeds

Low temperature CMOS (CRYO-CMOS) has been found to be especially suitable for VLSI based systems since it offers high density and low power dissipation. This paper will report on the performance of CRYO-CMOS 8×8b multipliers with 8ns multiplication time, and 5mW and 460mW power dissipation, respectively.