T. Masuhara

Operation of bulk CMOS devices at very low temperatures

Low-temperature (77K, 4.2K) operation is proposed for bulk CMOS devices to be used in superfast VLSI applications. Symmetrical variation of the parameters of both n-channel and p-channel MOSFETs with respect to the temperature and latch-up immunity makes CMOS a very promising device technology at low temperatures. To demonstrate the performance advantage of circuit operation at low temperatures, inverter chains and 16-kb static random-access memories (RAMs) with 2-/spl mu/m gate length were measured. Average propagation delay for an inverter chain has been reduced to 175 ps (77K) and 104 ps (4.2K) from 296 ps at 300K without sacrificing power dissipation. The power-delay product is less 1 fJ, which is the smallest for silicon devices reported to date. The chip select-access time of the RAM has been reduced to 14.3 ns (77K) from 24 ns (300K).

Performance and hot-carrier effects of small CRYO-CMOS devices

The performance characteristics of submicrometer CMOS devices operating at low/cryogenic temperatures (CRYO-CMOS) are determined. The advantages and problems in a CRYO-CMOS technology are experimentally studied in relation to the velocity saturation, source-drain resistances, mobility behavior, carrier freeze-out effects, hot-carrier effects, and circuit performance. The increase of the maximum transconductance at low temperatures (77, 4.2 K) has been confirmed even in the submicrometer channel region. However, improvement of inabilities at a VGnearly equal to 5 V is not so significant in devices with thinner oxides and less so in pMOS devices than in nMOS devices. Excellent subthreshold characteristics have been obtained at low temperatures, making very low-voltage operation possible. One problem found in the threshold control of pMOS transistors is that the boron ions implanted in the surface freeze out, causing unusual subthreshold behavior. Circuit delays have been improved by a factor of 2 to 3, and CRYO-CMOS shows the lowest power-delay product among existing semiconductor technologies with speed performance comparable to bipolar ECL devices. For LDD devices, speed improvements are only slightly smaller than for single-drain devices, while currents and transconductances in the linear regions are limited because of carrier freeze-out of the lightly doped drain. For both channel LDD devices, the transconductance degradations and VTshifts observed under dc stress conditions at 77 K are considered to result from electron injection into spacer oxides.

A 20ns 64K CMOS SRAM

A 19.0mm264K×1 SRAM utilizing pulsed-word-line technique, P-well/bipolar technology, and 1.3μm gate MOS transistors, will be described. The RAM has typical address access time of 20ns and power dissipation of 70mW at 1 MHz cycle time.

A high-performance N-channel MOS-LSI using depletion-type load elements

A design approach of the depletion-load inverter is given in which an attempt is made to obtain large noise margins. It is predicted that the circuit will operate with a 10-15 pJ/pF power- delay product at +5-V supply voltage. Some experimental integrated circuits were designed and fabricated by making use of a novel n-channel MOS technology that utilizes both enhancement and depletion-type MOSFET on a chip. A fully decoded transistor- transistor logic (TTL)-compatible READ-ONLY memory was fabricated, resulting in 300 ns total access time at a +5-V single power supply.

Low-temperature CMOS 8 × 8 bit multipliers with sub-10-ns speeds

Low-temperature (77, 4.2 K) operation is proposed for bulk CMOS devices for use in super-fast VLSI applications. Symmetrical variations of both types of MOSFET parameters with respect to temperature and latchup immunity make CMOS a very promising device technology at low temperatures. To demonstrate the performance advantage of circuit operation at low temperatures, multipliers with two different circuit configurations are designed and fabricated with a gate length of 1.3 µm. Multiplication speeds of 8.0 and 6.6 ns are obtained with CMOS circuit configurations at 4.2 K and with pulsed-p-load/CMOS circuit configurations at 77 K, respectively.

A 15ns 1mb Cmos Sram

ing of 512 rows and 64 columns and controlled by a word decoder. One word line is selected by a word decoder according to the selection signal from a pre-word-decoder. A high-speed word decoder is essential for fast access in this architecture. Figure 2 shows the circuit schematic of two word decoders using 8 PMOS-load NAND gates with a common lower stage NMOS. This has two advantages. First, the gate capacitances of the decoders connected to signal lines are reduced substantially, so that signal propagation delay is greatly decreased. Second, the number of PMOS and NMOS in NAND gates can be drastically reduced permitting a decoder width of 6 6 ~ . This is especially significant because the chip has 32 sets of word decoders. The same architecture is used for other decoders, including column and pre-word. This procedure contributes to achieving small chip size and fast access time. A sense amplifier design with three-stage dynamic gain is shown in Figure 3. Here, common data bus signals are amplified by two stages of paired current, mirror amplifiers and are transferred to the main data bus through transfer gates. Therefore, the main data bus is driven directly by the second stage of the sense amplifiers. The main data bus signals cannot rapidly reach large amplitudes because of the large stray capacitance of the main data bus, and must be amplified by a main amplifier located close to an output buffer. The gains of those amplifiers are dynamically controlled by switching the current using Address Transition Detector (ATD) pulses. This allows high sense speed with reduced average current.

A 256K CMOS SRAM with variable impedance data-line loads

A 256K (32K/spl times/8) CMOS SRAM utilizing variable impedance loads and a pulsed word-line (PWL) technique is described. In the WRITE cycle, the variable impedance loads of the data lines enter a high impedance state and reduce the operating power. During the READ cycle, the PWL technique is used to achieve high-speed operation and low power dissipation. The internal clocks generated by the address transition detectors activate word-line and sense amplifiers for READ operation and disable them after the data are sent to D/SUB out/ buffers. This PWL technique eliminates the precharge time of 20 ns, which corresponds to 30% of the access time. The RAM offers 45-ns address access time and 40-mW operating power in the WRITE cycle of 1 MHz.

A HI-CMOSII 8K × 8b static RAM

A fully-static 8K×8b RAM using HICMOSII technology with a typical address access time of 65ns and power dissipation of 200mW will be discussed. To improve manufacturing yield a laser redundancy technique utilizing a N+ -i-N+ polysilicon structure was employed.

A Hi-CMOSII 8Kx8 bit static RAM

A Hi-CMOSII static RAM with 8K word by 8 bit organization has been developed. The RAM is fabricated using double polysilicon technology and p- and n-channel transistors having a typical gate polysilicon length of 2 /spl mu/m. The device was realized using low-power high-speed-oriented circuit design and a new redundancy circuit that utilizes laser diffusion programmable devices. The new RAM has an address access time of 65 ns, operating power dissipation of 200 mW, and standby dissipation of 10 /spl mu/W.

HI-CMOSII 4K static RAM

This paper will discuss an 18ns/150mW fully static 4096×1b RAM, using double poly HI-CMOSII technology with 2μm gate length.