S. Koveshnikov
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Featured researches published by S. Koveshnikov.
Applied Physics Letters | 2006
S. Koveshnikov; W. Tsai; I. Ok; J. C. Lee; V. Torkanov; M. Yakimov; S. Oktyabrsky
We demonstrate the electrical properties of metal-oxide-semiconductor capacitors on molecular beam epitaxial GaAs in situ passivated with ultrathin amorphous Si (a-Si) layer and with ex situ deposited HfO2 gate oxide and TaN metal gate. Minimum thickness of the Si interface passivation layer of 1.5 nm is needed to prevent the Fermi level pinning and provide good capacitance-voltage characteristics with equivalent oxide thickness of 2.1 nm and leakage current of ⩽1.0mA∕cm2. Transmission electron microscopy analysis showed that the Si layer was oxidized up to 1.4 nm during ex situ processing while the interface between the GaAs and a-Si remained atomically sharp without any sign of interfacial reaction.
IEEE Transactions on Electron Devices | 2010
A. Ali; Himanshu Madan; S. Koveshnikov; S. Oktyabrsky; Rama Kambhampati; Darrell G. Schlom; Suman Datta
Ultrahigh-mobility compound semiconductor-based MOSFETs and quantum-well field-effect transistors could enable the next generation of logic transistors operating at low supply voltages since these materials exhibit excellent electron transport properties. While the long-channel In0.53 Ga0.47As MOSFETs exhibit promising characteristics with unpinned Fermi level at the InGaAs-dielectric interface, the high-field channel mobility as well as subthreshold characteristics needs further improvement. In this paper, we present a comprehensive equivalent circuit model that accurately evaluates the experimental small-signal response of inversion layers in In0.53 Ga0.47As MOSFETs fabricated with LaAlO3 gate dielectric and enables accurate extraction of the interface state profile, the trap dynamics, and the effective channel mobility.
international electron devices meeting | 2008
Niti Goel; Dawei Heh; S. Koveshnikov; I. Ok; S. Oktyabrsky; V. Tokranov; R. Kambhampatic; M. Yakimov; Yun Sun; P. Pianetta; C. K. Gaspe; M.B. Santos; J. C. Lee; Suman Datta; Prashant Majhi; W. Tsai
Through a detailed evaluation of various dielectrics, we address the primary challenges associated with gate stacks on high electron mobility InGaAs channels. More specifically we address key gate stack issues including a) EOT scalability for high performance and electrostatic control (this work CET ~0.78 nm) with acceptable leakage both at operating and offstate for low power (this work Jg ~1 A/cm2), b) understand source and impact of charge trapping, c) thermal stability on InGaAs, and d) impact of In% on interface structure and its impact on surface channel MOSFETs.
Applied Physics Letters | 2006
Hyoung Sub Kim; I. Ok; Manhong Zhang; T. Lee; F. Zhu; L. Yu; Jack C. Lee; S. Koveshnikov; W. Tsai; Vadim Tokranov; Michael Yakimov; S. Oktyabrsky
The authors present depletion-mode n-channel GaAs metal-oxide-semiconductor field-effect transistor (MOSFET) with a TaN gate electrode, a thin HfO2 gate dielectric, and a thin germanium (Ge) interfacial passivation layer (IPL). Depletion-mode MOSFET on the molecular-beam epitaxy-grown n-type GaAs layer with an equivalent oxide thickness of 17A exhibits excellent transistor output characteristics such as a maximum transconductance of 176mS∕mm and a maximum effective electron mobility of 970cm2∕Vs. MOSFET shows a surface accumulation channel conduction above flatband condition, indicating that a high quality interface can be achieved using a Ge IPL on GaAs substrate.
Journal of Vacuum Science & Technology B | 2007
I. Ok; Hyoungsub Kim; Manhong Zhang; F. Zhu; S. Park; Jung Hwan Yum; S. Koveshnikov; W. Tsai; Vadim Tokranov; Michael Yakimov; S. Oktyabrsky; Jack C. Lee
Recently, the authors have investigated the GaAs metal-oxide-semiconductor field-effect transistor using Si interface passivation layer (IPL) and HfO2 as gate dielectric. In this work, they have investigated InGaAs MOSCAP using the same oxide of HfO2 as gate insulator with Si IPL. In this work, the authors studied the effects of postdeposition anneal (PDA) time and Si IPL on the electrical characteristics of the metal-oxide-semiconductor capacitor with high-k (HfO2) material on InGaAs. Excellent electrical characteristics with thin equivalent oxide thickness (∼2.5nm), low frequency dispersion (<5%) have been obtained. The thickness of the Si IPL and PDA time were correlated with C-V characteristics.Recently, the authors have investigated the GaAs metal-oxide-semiconductor field-effect transistor using Si interface passivation layer (IPL) and HfO2 as gate dielectric. In this work, they have investigated InGaAs MOSCAP using the same oxide of HfO2 as gate insulator with Si IPL. In this work, the authors studied the effects of postdeposition anneal (PDA) time and Si IPL on the electrical characteristics of the metal-oxide-semiconductor capacitor with high-k (HfO2) material on InGaAs. Excellent electrical characteristics with thin equivalent oxide thickness (∼2.5nm), low frequency dispersion (<5%) have been obtained. The thickness of the Si IPL and PDA time were correlated with C-V characteristics.
Journal of Applied Physics | 2007
Manhong Zhang; M. Oye; Brian Cobb; Feng Zhu; Hyoung-Sub Kim; I. Ok; J. Hurst; S. Lewis; A. L. Holmes; J. C. Lee; S. Koveshnikov; W. Tsai; Michael Yakimov; V. Torkanov; S. Oktyabrsky
The interfacial change of HfO2∕Si∕n-GaAs gate stacks after high temperature annealing has been characterized using x-ray photoelectron spectroscopy (XPS), photoluminescence (PL), and capacitance-voltage measurement. The properties of the interface are sensitive to the amount of incorporated oxygen. XPS measurement shows the formation of gallium and arsenic oxides with increasing annealing temperature. A PL emission from the Si interfacial passivation layer was observed after 900°C annealing. With more oxygen incorporation, this PL emission was quenched. The measurement of the interface state density proved the generation of deep traps with too much oxygen incorporation. Depletion-mode metal-oxide-semiconductor field effect transistors using postdeposition annealing at 600°C with and without post-metal-annealing at 900°C have also been fabricated and characterized. Too much oxygen incorporation resulted into the degradation of mobility, subthreshold swing, and transconductance. The interfacial gallium and ...
device research conference | 2008
S. Koveshnikov; Niti Goel; Prashant Majhi; C. K. Gaspe; M. B. Santos; S. Oktyabrsky; Vadim Tokranov; Michael Yakimov; R. Kambhampati; H. Bakhru; F. Zhu; J. C. Lee; W. Tsai
Self-aligned MOSFETs with high-Indium content InGaAs based channel, ultra-thin high-k dielectric and metal gate are attractive devices for logic applications. To be compatible with the future generation CMOS technology, these devices must demonstrate high channel mobility and excellent performance at low operating voltage. Development of a thermally stable I-V/high-k interface with low EOT and low interface state density remains the key challenge for compound semiconductor implementation.
compound semiconductor integrated circuit symposium | 2008
Feng Zhu; Han Zhao; I. Ok; Hyoung-Sub Kim; Manhong Zhang; S. Park; Jung Hwan Yum; S. Koveshnikov; Vadim Tokranov; Michael Yakimov; S. Oktyabrsky; W. Tsai; Jack C. Lee
Charge trapping and wearout characteristics of self-aligned enhancement-mode GaAs nMOSFETs with silicon interface passivation layer and HfO2 gate oxide are systematically investigated at various time scales (from micro-seconds to seconds). Unlike high-kappa on silicon devices, both bulk trapping and interface trapping affect the PBTI (positive bias temperature instability) characteristics of nMOSFETs. The comparison between pulsed Id-Vg and conventional DC measurements reveals that the intrinsic characteristics of GaAs transistors absent of transient charging effects can be much better than what have been observed in DC based test. The electron trapping process is found to be faster than de-trapping process. The results suggest that suppressing charge trapping in gate dielectrics is critical to implement high performance and reliable III-V MOSFETs for digital logic applications in post- silicon era.
International Journal of High Speed Electronics and Systems | 2008
S. Oktyabrsky; Michael Yakimov; Vadim Tokranov; Rama Kambhampati; H. Bakhru; S. Koveshnikov; W. Tsai; Feng Zhu; Jack C. Lee
An overview of III-V MOSFET technological challenges in comparison to well-established heterostructure-based FET technologies is presented with an emphasis on required properties and possible solutions. Possible approaches to achieve thermodynamically stable high-k gate stack with low interface trap density are reviewed, followed with our results on amorphous Si interface passivation layer (IPL) in-situ deposited on top of GaAs or strained InGaAs MOSFET channels grown by molecular beam epitaxy. Main issues of Si IPL, namely increased equivalent oxide thickness due to IPL oxidation and Si diffusion into the semiconductor channel, are addressed using an in-situ deposited HfO2 with ultrathin (down to 0.25 nm) Si IPL and controlling its bonding state at the interface. Enhancement mode inversion-type MOSFET with HfO2 high-k oxide is demonstrated. The device employs amorphous Si interface passivation layer, sputter-deposited high-k oxide and metal TaN gate and modulation p-doped GaAs/AlGaAs heterostructure with inversion n-channel formed at the interface with the oxide. The MOSFET with equivalent oxide thickness of 3.7 nm and long 100 μm channel have maximum DC transonductance of 0.9 mS/mm, Ion/Ioff = 2×104 (at low Ioff of 30 nA) and effective channel mobility exceeding 1000 cm2/V-s at sheet electron density <2×1012 cm-2.
Archive | 2010
S. Oktyabrsky; Yoshio Nishi; S. Koveshnikov; Wei-E Wang; Niti Goel; Wilman Tsai
The paper contains an overview of progress and challenges of group III-V MOSFETs. It begins with comparison of well-established high-electron mobility transistors for logic applications to MOSFET technology. Further, the results on improvement of current transport in buried modulation doped quantum well channels similar to HEMTs are presented. Next, the progress in interface passivation is reviewed, and detailed with descriptions of different technologies including atomic layer deposition with its property to self-clean a III-V surface, amorphous Si and Ge passivation, and use of in-situ high-k oxide deposition.