C. Ndiaye

Impact of gate oxide breakdown in logic gates from 28nm FDSOI CMOS technology

For advanced CMOS nodes, high performance is reached with the down scaling of both critical gate length and dielectrics stack. The aggressive reduction of dielectric thickness leads to a reduction of reliability margin due to breakdown. However, the first breakdown (BD) event does not always cause a functional failure in digital circuits. Lifetime extension based on device level parameters drift is difficult to handle, an accurate BD model is thus mandatory for predictive simulations at circuit level. Two dedicated test structures have been designed to track BD events impact on logic gates. Different AC-DC conditions are examined to be closer to operating conditions of digital circuits. Then a compact model for BD in logic gates is proposed: according to device level measurements, different severities of the BD event impact can be selected. Next Monte Carlo simulations are performed and enable to discuss the real impact of BD on logic gates in comparison with the measurements. In this way the measurements at device and circuit levels can be linked and the most likely post-BD device characteristics are highlighted. Therefore, the real impact of hard BD can be mitigated.

New insights on strained SiGe channels pFET NBTI reliability

This work provides new results on the effects of the variation of Length of Diffusion (LOD), for active zones, the concentration of Germanium (Ge) and the impact of gate stack variation found on the performance and reliability in p-MOSFET transistors fabricated with a 14nm Ultra-Thin Body and Box (UTBB) FDSOI CMOS technology. Experiments show that changing the gate-to-STI distances on active (SA) or Germanium concentration has an impact on threshold Voltage (Vth), and on NBTI reliability. This study offers new perspectives to understand the impact of SiGe on NBTI degradation and recovery. Furthermore we show that NBTI recovery is not impacted neither by SiGe concentration nor gate stack and we also see that SiGe allows to improve NBTI degradation.

Layout Dependent Effect: Impact on device performance and reliability in recent CMOS nodes

In this paper, we analyze the impact of Layout Dependent Effect (LDE) observed on MOSFETs. It is shown that changing the Layout have an impact on MOSFET device parameters and reliability. Here, we studied the Well Proximity Effect (WPE), Length of diffusion (LOD) and Oxide Spacing Effect (OSE) impacts on device MOSFET parameters and reliability. We also analyzed SiGe impacts on LDE, since it is commonly used to boost device performance.

Reliability compact modeling approach for layout dependent effects in advanced CMOS nodes

In this paper, we have analysed and modelled the layout dependent effects (LDE) found in pMOSFET transistors from 14nm UTBB FDSOI CMOS technology. Experiments show that changing the layout has a clear impact on threshold Voltage (Vth), under NBTI reliability and on Ring Oscillator (RO) Frequency drift. Compact models taking account the impact of LDE on Vth, NBTI reliability, and on RO frequency are proposed. Measurement data are fitted with a new compact model showing that the obtained results are in very good agreements with the modelling.

Improved analysis of NBTI relaxation behavior based on fast I–V measurement

In this paper, we propose a qualitative analysis of NBTI recoverable components measured on pFET devices issued from various ST Microelectronics (28nm FDSOI technology and 40nm SION or Bulk) technologies. NBTI degradation and recovery resulting from DC stress are measured at µs time scale. We observed similarities between temperature and Vgrecovery dependencies on NBTI relaxation of SiON and FDSOI technologies. Then, we discuss the nature of one defect type responsible for the NBTI at early stage of relaxation.

Potentiality of healing techniques in hot-carrier damaged 28 nm FDSOI CMOS nodes

We have developed the possibility of using healing phases on hot-carrier (HC) degraded transistors from devices to logic cells (1) by the combined effects of oxide charge neutralization and channel shortening (2) using back bias V-B sensing effects in forward (FBB) mode in 28 nm FDSOI CMOS node. This is done for DC to AC operations from Input-Output device (EOT = 3.6 nm) to core blocks (EOT = 135 nm) leading to an almost complete cure of HC damaged devices for digital application. Continuous or short sequences of healing phases help to regenerate HC degraded parameters (I-on, V-T) offering new perspectives for on time repeatedly cure digital operation as well as under some analog case