S. Okhonin

Transient effects in PD SOI MOSFETs and potential DRAM applications

Abstract The transients in partially depleted (PD) silicon on insulator (SOI) MOSFETs produced with 0.25 and 0.13 μm technologies are studied. The exponential dependence of the switch-on transient time on the reciprocal drain voltage for both P- and N-channel devices is explained by the predominance of the impact ionisation mechanism. A pulse method to measure output I – V curves using short gate pulses has been applied to study self-heating and transient effects in 0.13 μm SOI N-MOSFETs. It is shown that under normal operating conditions the difference between DC and pulsed I – V curves of PD SOI MOSFET is attributed mainly to the floating body effect and not to self-heating. We demonstrate also that it is possible to use the body charging of PD SOI devices to store information. Based on this effect, an original 1T-DRAM cell concept is proposed (DRAM: dynamic random access memory). This cell is at least two times smaller in area than the conventional 1T/1C DRAM cell and does not require the integration of a storage capacitor. This concept allows the manufacture of low cost DRAMs and embedded DRAMs for 100 and sub-100 nm generations.

Highly manufacturable capacitor-less 1T-DRAM concept

We introduce a new cell architecture for Dynamic Random Access Memory (DRAM) and embedded DRAM applications. By exploiting the Floating Body characteristics of partially depleted silicon on insulator (SOI) transistors, a capacitor-less DRAM cell structure can store and amplify the stored signal by using only a single transistor. Such a DRAM cell has a footprint two times smaller than that of standard DRAM cells and can be integrated in any CMOS process.

DC and low-frequency noise characteristics of SiGe p-channel FETs designed for 0.13-/spl mu/m technology

The impact of hole confinement on the DC and low frequency noise in SiGe p-channel FETs is investigated by comparison with Si p-FETs produced by the same technology. The relative spectral power density of low frequency (1/f) noise in SiGe pFETs is found to be significantly lower than in Si devices. This is mainly attributed to the physical separation of the holes confined in the SiGe channel from the Si/SiO/sub 2/ interface. The low value of SiGe channel noise proves the good quality of epilayers and heterointerfaces, as also revealed by the TEM cross section.

Comparison of gate-induced drain leakage and charge pumping measurements for determining lateral interface trap profiles in electrically stressed MOSFETs

Improved methods for extracting lateral spatial profiles of interface traps in electrically stressed MOSFETs from gate-induced drain leakage and charge pumping measurements are proposed. Simplified theoretical models are developed. The formal similarity of the two methods is shown. The results obtained on submicron MOSFET after uniform (Fowler-Nordheim) and nonuniform (hot carrier) stress are compared and found to be in good agreement. The relative merits of these techniques are discussed.

Low-frequency noise in electrically stressed n-MOSFETs

Abstract Low-frequency noise, electrical current–voltage characteristics and charge pumping methods were employed to study the time-dependent degradation behavior of n -MOSFETs. The increase of 1/ f noise under stress correlates, in a non linear manner, with the increase in charge pumping current and the decrease in maximum DC transconductance. The degradation of 1/ f noise was found to be an exponential function of the degradation of maximum transconductance, which indicates that the noise can be used as a sensitive monitor for device degradation.

Two-band tunneling currents in metal-oxide-semiconductor capacitors at the transition from direct to Fowler–Nordheim tunneling regime

The conduction and valence band tunneling currents in ultrathin SiO2 films are studied. The slopes of the current–voltage characteristic agree well with the simulations performed. Conduction band current oscillations due to interference of the electrons from the inversion channel at the oxide/gate interface are observed. The shape of the slope of the valence band current in Fowler–Nordheim regime can be explained by the interference of the valence band electron wave at the oxide/gate interface.

Spatial distribution of interface traps after hot-carrier stress from forward GIDL measurements

Abstract The feasibility of extracting the spatial distribution of interface traps from forward gate-induced drain leakage (GIDL) measurements on submicron MOSFETs is demonstrated. The results of this technique are similar to those of the charge pumping (CP) one. The differences between the two techniques are discussed.

Transient effects in PD SOI NMOSFETs

We investigated the transients in 0.25 μm PD SOI devices. A good agreement between experimental and simulation results has been observed. The exponential dependence of the switch-on transient time on the reciprocal drain voltage for both p- and n-channel devices is explained by the predominance of the impact ionisation mechanism.

An extended model for soft breakdown in ultra-thin SiO/sub 2/ films

This paper presents a complete picture of soft breakdown (SBD) including the behavior of conduction and valence band currents. This picture relies on trap-assisted inelastic conduction through deep traps. New electron energy loss data after SBD strongly support the model we also report an energy loss of 0.8 eV for SILC-electrons in 3.6 nm oxide film.

Single Trap Profiling by Charge Pumping

We demonstrate that the CP characteristic of a single trap can be measured in relatively large MOSFETs or even in arrays of MOSFETs with common gates, common sources and separated drain contacts where the total quantity of interface traps can be as high as several thousands. The influence of CP parameters is also demonstrated. The possibility to use these results to study the influence of single trap on the GIDL is discussed.