S. Ramey

BTI reliability of 45 nm high-K + metal-gate process technology

In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and final HK process demonstrated NMOS and PMOS BTI on HK+MG transistors that are better than that of SiON at matched E-fields and comparable at targeted 30% higher use fields. The final process also showed no hysteresis due to fast traps thereby allowing us to characterize its intrinsic degradation mechanism. On the optimized process, NMOS BTI is attributed primarily to electron trapping in the HK bulk and HK/SiON interfacial layer (IL) regions. PMOS BTI degradation, on the other hand, is mainly interface driven and is found to be very similar to that observed on conventional SiON transistors.

Intrinsic transistor reliability improvements from 22nm tri-gate technology

This paper highlights the intrinsic reliability capabilities of Intels 22nm process technology, which introduced the tri-gate transistor architecture and features a 3rd generation high-κ/metal-gate process. Results are detailed from all traditional transistor reliability mechanisms, including BTI, TDDB, SILC, and HCI. In addition, characteristics unique to this transistor architecture and process technology are described.

Frequency and recovery effects in high-κ BTI degradation

Net end-of-life aging prediction under realistic use conditions is the key objective for any product aging model. In this paper, a net degradation model is introduced and effects such as recovery, subsequent degradation, frequency, duty cycle, and recovery bias are evaluated. The high-κ recovery behavior observed is consistent with SiO2 gate stacks, which allows the use of SiO2 models to predict recovery in both NMOS and PMOS high-κ transistors.

Self-heat reliability considerations on Intel's 22nm Tri-Gate technology

This paper describes various measurements on self-heat performed on Intels 22nm process technology, and outlines its reliability implications. Comparisons to thermal modeling results and analytical data show excellent matching.

Bias temperature instability variation on SiON/Poly, HK/MG and trigate architectures

A summary of NBTI variation is reported on large data-sets across five generations of Intel technologies (90 nm to 22 nm) and a comparison of statistical frameworks is utilized to show the universality of variation metrics across generations. Large volumes of data and modeling are emphasized as critical to enable accurate simulations of NBTI in extreme tails.

Dielectric breakdown in a 45 nm high-k/metal gate process technology

In this paper, we present extensive breakdown results on our 45nm HK+MG technology. Polarity dependent breakdown and SILC degradation mechanisms have been identified and are attributed gate and substrate injection effects. Processing conditions were optimized to achieve comparable TDDB lifetimes on HK+MG structures at 30% higher E-fields than SiON with a reduction in SILC growth. Extensive long-term stress data collection results and a change in voltage acceleration are reported.

Transistor aging and reliability in 14nm tri-gate technology

This paper details the transistor aging and gate oxide reliability of Intels 14nm process technology. This technology introduces Intels 2nd generation tri-gate transistor and the 4th generation of high-κ dielectrics and metal-gate electrodes. The reliability metrics reported here highlight reliability gains attained through transistor optimizations as well as intrinsic challenges from device scaling.

Transistor reliability variation correlation to threshold voltage

MOSFET reliability data are often represented as a function of gate overdrive (VG-VT) with the implicit assumption that overdrive is the appropriate normalizing parameter. While this can be true for some specific sources of variation, reliability does not necessarily track gate overdrive. This paper explores systematic and random sources of variation in TDDB, BTI, and hot carrier degradation data in Intels tri-gate technologies. We find that random variation captured within a baseline of reliability data does not, in general, trend with overdrive. However, some sources of systematic variation are correlated or, interestingly, anti-correlated with overdrive.

Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology

Transition into High-K (HK) dielectric and Metal-Gate (MG) in advanced logic process has enabled continued technology scaling in support of Moores law [1-2]. With this, CMOS operating fields have been increasing along with gate dielectric TDDB voltage acceleration factors (VAF). VAF is the most critical reliability parameter used to accurately predict the Gate oxide lifetime (TDDB) at use. This paper highlights low voltage (low-V) TDDB data is critical for the accurate assessment of HK+MG VAF and provides further evidences from both transistor- and product-level data based on 32nm technology generations.

BTI recovery in 22nm tri-gate technology

BTI recovery in tri-gate devices matches data and model predictions from planar devices, indicating a consistent physical basis for the mechanism and no influence from transistor architecture features such as crystal orientation, confinement, and vertical sidewalls. This consistency enables extending existing models established on planar devices to capture temperature and voltage dependencies of recovery. A new experimental technique allows extraction of an effective activation energy for recovery. The observation of complete recovery demonstrates that no permanent damage occurs during stress.