Myoung-Bum Lee

Epitaxial growth of Y2O3 films on Si(100) without an interfacial oxide layer

Heteroepitaxial Y2O3 films were grown on Si(100) substrates by the technique of reactive ionized cluster beam deposition. The crystallinity of the films was investigated with reflection high energy electron diffraction (RHEED), glancing angle x-ray diffraction (GXRD), and the interface was examined by high resolution transmission electron microscopy (HRTEM). Under the condition of 5 kV acceleration voltage at the substrate temperature of 800 °C, the Y2O3 film grows epitaxially on the Si(100) substrate. RHEED and GXRD results revealed that the epitaxial relationship between Y2O3 and Si(100) is Y2O3(110)//Si(100), and HRTEM observation showed a sharp interface without an amorphous layer.

Highly manufacturable process technology for reliable 256 Mbit and 1 Gbit DRAMs

Ta/sub 2/O/sub 5/ dielectric on poly-Si cylinder capacitors, chemical-mechanical polishing (CMP) planarization, pure W bit-line, and Al reflow were integrated into a highly manufacturable DRAM process technology. This technology provided larger process margin, higher reliability, and better design flexibility. In addition, the critical steps of the new process has been reduced by 25% of those of the conventional process. The manufacturability of the technology has been proven by applying it to 16 Mbit density DRAMs with 256 Mbit design rule (0.28 /spl mu/m).<<ETX>>

Advanced plasma technology in microelectronics

Abstract The current status and future trends of plasma technology for microelectronics are discussed. The low pressure high density plasma (HDP) source is advantageous for the etching of a gate electrode and a small deep contact hole. However, the high temperature electrons in the HDP may induce profile defects, notch and sidewall etching, and may degrade the electrical quality of the gate oxide. By lowering the electron temperature with the pulse plasma technique, the etch profile of the gate electrode was improved. Platinum, the suggested storage electrode for the capacitor of the next generation ULSI, was etched in a magnetically enhanced reactive ion etching (MERIE) plasma. With the etching chemistry of Cl2/O2/Ar, it was etched with the slope of up-to 80°. In SiO2 etching, the HDP is advantageous for less RIE-lag. We also need to control the polymerization for the critical dimension (CD) control and for the selectivities to the resist, silicon, and also to Si3N4 for the self-aligned contact (SAC). It was shown that it is possible to control the dissociation of radicals in the plasma and the surface reaction with a phase-controlled pulse plasma. The chemistry C4F8/CH3F/Ar was shown to achieve the requirements for the SAC hole etching, but the process window was quite narrow. Also, the HDP-CVD SiO2 and SiOF have shown better gap filling capability, film quality and more favorable deposition profiles than conventional CVD oxides. We also discussed the results of the application of HDP-CVD oxide to the trench isolation and the intermetal dielectrics (IMDs). The film characteristics of fluorine doped HDP-CVD SiO2 (SiOF) as a low dielectric material was found to be very stable with uniform film properties even after high temperature stressing at 350°C for 100 h.

Stress minimization in deep sub-micron full CMOS devices by using an optimized combination of the trench filling CVD oxides

We have found that the defect generation which is induced by the mechanical stress during the densification, depends on the ratio of the trench filling material composed of the TEOS-O/sub 3/ based CVD oxide with tensile stress and the plasma enhanced CVD oxide with compressive stress. The lower as-deposited stress is, the lower the maximum stress during the densification is. This stress level is proportional to the defect density which is generated in fabricating MOSFETs with Shallow Trench Isolation (STI). In order to achieve devices without a defect, it is important to minimize as-deposited stress level by optimizing the ratio of the trench filling CVD oxides.

CMOS device scaling beyond 100 nm

CMOS device scaling beyond 100 nm has been investigated. Issues on scaling and previous works to solve them were reviewed. Super steep retrograde channel formation using selective epitaxial growth of undoped silicon effectively suppressed short channel effect and improved transconductance. The stack gate dielectrics of oxynitride and nitride suppressed boron penetration and improved drive currents. Transistor characteristics and reliability issues on gate oxide scaling were investigated in the regime of large gate leakage currents. High performance CMOS transistors of L/sub gate/=70 nm and T/sub ox/=1.4 nm were fabricated, which showed current drives of 860 /spl mu/A//spl mu/m (NMOS) and 350 /spl mu/A//spl mu/m (PMOS) at I/sub off/=10 nA//spl mu/m and V/sub dd/=1.2 V.

A novel Al-reflow process using surface modification by the ECR plasma treatment and its application to the 256 Mbit DRAM

A novel Al-reflow process with the electron cyclotron resonance (ECR) plasma treatment for the modification of underlayers was developed in a vacuum isolated sputtering equipment. The key feature of this technology is the introduction of the in-situ ECR plasma treatment for the modification of the surface characteristics such as surface morphology and stoichiometry of the TiN wetting/barrier layer. High wettability of the Al film was obtained on the ECR-treated TiN surface, producing a conformal Al film on the sidewall of the contact hole before the reflow process. Consequently, complete filling of contact holes with Al was achieved in deep sub-micron contact holes with a high aspect ratio. This study has demonstrated that the Al-reflow process can be extended to the process of the devices of 256 Mbit DRAM generation and beyond.<<ETX>>

High performance pMOSFET with BF/sub 3/ plasma doped gate/source/drain and S/D extension

A BF/sub 3/ Plasma doping (PLAD) process has been utilized in source/drain/gate and shallow S/D extension for high performance 0.18 /spl mu/m pMOSFET. Gate oxide reliability, drain current, and transconductance of the pMOSFET with BF/sub 3/ PLAD are remarkably improved compared to those of BF/sub 2/ ion implanted devices. Cobalt salicide formation is also compatible with the plasma doped S/D junction.

Heteroepitaxial growth of Y2O3 films on Si(100) by reactive ionized cluster beam deposition

Abstract Heteroepitaxial Y 2 O 3 films on Si(100) have been grown by the technique of reactive ionized cluster beam (ICB) deposition. The composition of deposited film is investigated by using the X-ray photoelectron spectroscopy (XPS). It was found that the composition ratio of Y to O is 1 to 1.46. Using reflection high energy electron diffraction (RHEED) and glancing angle X-ray diffraction (GXRD), we study the crystallinity of the films. It was noticed that the orientation of deposited film is mainly determined by the substrate temperature and the cluster acceleration energy. We also found that, without acceleration below 800°C, Y 2 O 3 films were grown as polycrystalline. Under the condition of 5 kV acceleration voltage above 650°C, we noticed the heteroepitaxial growth of Y 2 O 3 film on Si(100) substrate. The epitaxial relationship between Y 2 O 3 and Si(100) is presented as Y 2 O 3 (110)//Si(100) and Y 2 O 3 [110]//Si[100] or Y 2 O 3 (110)//Si(100) and Y 2 O 3 [100]//Si[100].

A novel simple shallow trench isolation (SSTI) technology using high selective CeO/sub 2/ slurry and liner SiN as a CMP stopper

A novel simple shallow trench isolation technology, SSTI, has been developed. SSTI consists of direct trench etching masked only with the photoresist, trench oxidation, liner SiN deposition, CVD oxide trench fill, densification, and high selectivity CMP. CMP stops at the liner SiN with a residual SiN thickness range of less than 2 nm and without micro-scratching. High selectivity CMP eliminates the field recess variation which is one of the drawbacks of conventional STI. SSTI is a promising candidate for future isolation technology.

Self-Aligned LOCOS/Trench (SALOT) combination isolation technology planarized by chemical mechanical polishing

A novel isolation technology of Self-Aligned LOCOS/Trench (SALOT) has been developed for the isolation of deep-sub micron devices. SALOT has the isolation structure of a Poly-Buffered LOCOS (PBL) field oxide and a self-aligned trench at the center of a narrow field region planarized by the Chemical Mechanical Polishing (CMP) process. With SALOT, dishing was effectively suppressed for field regions as wide as 4 mm. Devices with SALOT show excellent isolation characteristics and gate oxide quality, and low leakage currents. SALOT can be scaled down to the 1 Gbit DRAM generation.<<ETX>>