Sunetra K. Mendis

CMOS active pixel image sensor

A new CMOS active pixel image sensor is reported. The sensor uses a 2.0 /spl mu/m double-poly, double-metal foundry CMOS process and is realized as a 128/spl times/128 array of 40 /spl mu/m/spl times/40 /spl mu/m pixels. The sensor features TTL compatible voltages, low noise and large dynamic range, and will be useful in machine vision and smart sensor applications. >

Update on focal-plane image processing research

An update on research activities at Columbia University in the area of focal-plane image processing is presented. Two thrust areas have been pursued: image reorganization for image compression and image half-toning. The image reorganization processor is an integration of a 256 X 256 frame-transfer CCD imager with CCD-based circuitry for pixel data reorganization to enable difference encoding for hierarchical image compression. The reorganization circuitry occupies 2 of the total chip area and is performed using three parallel-serial-parallel (SP3) registers, a pixel resequencing block, and a sampling block for differential output. The chip has achieved a CTE of 0.99994 in this new SP3 architecture, at an output rate of 83 X 103 pixels/sec. (0.9996 at 2 X 106 pixels/sec) and an overall output amplifier sensitivity of 3.2 (mu) V/electron. The half-toning chip design has been described previously, and consists of a 256 X 256 frame transfer imager, a pipeline register, and comparator circuit. Functional testing of these elements is reported at this time.

Progress in CMOS Active Pixel Image Sensors

Recent research results regarding the investigation of CMOS active pixel image sensors (APS) are reported. An investigation of various designs for the pixel, including photogate devices of various geometries and photodiode devices, has been performed. Optoelectronic performance including intrapixel photoresponse maps taken using a focused laser scanning apparatus are presented. Several imaging arrays have also been investigated. A 128 X 128 image sensor has been fabricated and characterized. Both p-well and n-well implementations have been explored. The demonstrated arrays use 2 micrometers CMOS design rules and have a 40 X 40 micrometers pixel pitch. Typical design fill-factor is 26%. Output sensitivity is 3.7 (mu) V/e- for the p-well devices and 6.5 (mu) V/e- for the n-well devices. Read noise is less than 40 e- rms for the baseline designs. Dynamic range has been measured to be over 71 dB using a 5 V supply voltage. The arrays are random access with TTL control signals. Results regarding on-chip suppression of fixed pattern noise also are presented.

Low-light-level image sensor with on-chip signal processing

The design of a low-light-level CMOS active-pixel-sensor (APS) with on-chip, semi-parallel analog-to-digital (A/D) conversion is presented. The imager consists of a 128 X 128 array of active pixels at a 50 micrometers pitch. Each column of pixels shares a 10-bit A/D converter based on first-order oversampled sigma-delta ((Sigma) -(Delta) ) modulation. The 10-bit outputs of each converter are multiplexed and read out through a single set of outputs. A semi-parallel architecture is chosen to achieve 30 frames/second operation even at low light levels. The sensor is designed for less than 10 e- rms noise performance. A 28 X 28 active-pixel-sensor (APS) with 40 X 40 micrometers 2 pixels as well as individual elements of the sigma-delta modulator have been fabricated and tested using MOSIS* 2 micrometers CMOS technology.

Low-power low-noise analog circuits for on-focal-plane signal processing of infrared sensors

On-focal-plane signal processing circuits for enhancement of IR imager performance are presented. To enable the detection of high background IR images, an in-pixel current-mode background suppression scheme is presented. The background suppression circuit consists of a current memory placed in the feedback loop of a CTIA and is designed for a thousand-fold suppression of the background flux, thereby easing circuit design constraints, and assuring BLIP operation even with detectors having large response non-uniformities. For improving the performance of low-background IR imagers, an on-chip column-parallel analog-to-digital converter (ADC) is presented. The design of a 10-bit ADC with 50 micrometers pitch and based on sigma-delta ((Sigma) -(Delta) ) modulation is presented. A novel IR imager readout technique featuring photoelectron counting in the unit cell is presented for ultra-low background applications. The output of the unit cell is a digital word corresponding to the incident flux density and the readout is noise free. The design of low-power (< 5 (mu) W), sub-electron input-referred noise, high-gain (> 100,000), small real estate (60 micrometers pitch) self-biased CMOS amplifiers required for photon counting are presented.

Design of a Low-Light-Level Image Sensor with On-Chip Sigma-Delta Analog-to- Digital Conversion

The design and projected performance of a low-light-level active-pixel-sensor (APS) chip with semi-parallel analog-to-digital (A/D) conversion is presented. The individual elements have been fabricated and tested using MOSIS* 2 micrometers CMOS technology, although the integrated system has not yet been fabricated. The imager consists of a 128 X 128 array of active pixels at a 50 micrometers pitch. Each column of pixels shares a 10-bit A/D converter based on first-order oversampled sigma-delta ((Sigma) -(Delta) ) modulation. The 10-bit outputs of each converter are multiplexed and read out through a single set of outputs. A semi- parallel architecture is chosen to achieve 30 frames/second operation even at low light levels. The sensor is designed for less than 12 e- rms noise performance.