Safina Hussain

Characterization of microprocessor chip stress distributions during component packaging and thermal cycling

On-chip piezoresistive stress sensors represent a unique approach for characterizing stresses in silicon die embedded within complicated packaging architectures. In this work, we have used test chips containing such sensors to measure the stresses induced in microprocessor die after various steps of the assembly process, as well as to continuously characterize the in-situ die surface stress during slow temperature changes and thermal cycling experiments. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. Finally, a metallic lid was attached to complete the ceramic LGA package. After every packaging step (solder reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. A set of low stress test fixtures was developed to eliminate clamping induced stresses being generated during the sensor resistance measurements. The build-up of the die stresses was found to be monotonically increasing, and the relative severity of each assembly step was judged and compared. In addition, finite element models of the packaging process were developed and correlated with the test chip data. This combined approach allowed for various material sets (solders, underfills, TIM materials, lid metals, and lid adhesives) to be analyzed and rated for their contribution to the die stress level. After first level packaging of the chips on the ceramic chip carriers, experiments have been performed to analyze the effects of slow (quasi-static) temperature changes and thermal cycling on the die stresses. Thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time.

Four-Wire Bridge Measurements of Silicon van der Pauw Stress Sensors

Under the proper orientations and excitations, the transverse output of rotationally symmetric four-contact van der Pauw (VDP) stress sensors depends upon only the in-plane shear stress or the difference of the in-plane normal stresses on (100) silicon. In bridgemode, each sensor requires only one four-wire measurement and produces an output voltage with a sensitivity that is 3.16 times that of the equivalent resistor rosettes or bridges, just as in the normal VDP sensor mode that requires two separate measurements. Both numerical and experimental results are presented to validate the conjectured behavior of the sensor. Similar results apply to sensors on (111) silicon. The output voltage results provide a simple mathematical expression for the offset voltage in Hall effect devices or the response of pseudo Hall-effect sensors. Bridge operation facilitates use of the VDP structure in embedded stress sensors in integrated circuits. [DOI: 10.1115/1.4028333]

Application of stress sensing test chips to area array packaging

Thermal cycling accelerated life testing is often used to qualify area array packages (e.g. Ball Grid Arrays and Flip Chip) for various applications. Finite element life predictions for thermal cycling configurations are challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In our research, we are using test chips containing piezoresistive stress sensors to continuously characterize the in-situ die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PBGA) components, ceramic ball grid array (CBGA) components, and flip chip on laminate assemblies. The utilized (111) silicon test chips are able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The die stresses are initially measured at room temperature after packaging. The assemblies are then subjected to thermal cycling over various temperature ranges including 0 to 100 °C, −40 to 125 °C, and −55 to 125 °C, for up to 3000 thermal cycles. During the thermal cycling, sensor resistances at critical locations on the die device surface (e.g. the die center and die corners) are recorded. From the resistance data, the stresses at each site can be calculated and plotted versus time. The experimental observations show significant cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of thermal cycling duration are also being correlated with the observed delaminations at the die surface (as measured using scanning acoustic microscopy (C-SAM)) and finite element simulations that include material constitutive models that incorporate thermal aging effects.

Error analysis for piezoresistive stress sensors used in flip chip packaging

Multi-element resistor rosettes on silicon are widely utilized to measure integrated circuit die stress in electronic packages and other applications. Past studies of many sources of error have led to rosette optimization and demonstrated that temperature-compensated stress extraction should be used whenever possible. In this work, we extend the error analysis to include the inherent uncertainty in the measured values of the sensor resistances and the temperature at time of the measurement. The stresses in an under-filled flip chip package are calculated using finite element simulation and utilized to evaluate the stress dependent sensitivities across the die surface. Monte Carlo simulation results confirm that temperature compensated rosette configurations should be utilized whenever possible.

Characterization of Compressive Die Stresses in CBGA Microprocessor Packaging Due to Component Assembly and Heat Sink Clamping

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials (TIMs), second level ceramic ball grid array (CBGA) solder joints, organic printed circuit board, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high coefficient of thermal expansion (CTE) ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state at each sensor site being monitored by the data acquisition hardware. Special test fixtures were developed to eliminate any additional stresses due to clamping effects. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, and lid attachment). The experimental observations from this study show clearly that large area array flip chips are subjected to relatively large compressive in-plane normal stresses after solder reflow. We also observed that the majority of the die compressive stress is accumulated during the underfilling assembly step. Typical increases in the stress magnitude were on the order of 300% (relative to the stresses due to solder joint reflow only). As a general “rule of thumb,” approximately two-thirds (∼66%) of the final die stress magnitudes were observed to be developed during the underfill dispense and cure, with the second largest contribution coming from the die attachment, and the smallest contribution coming from lid attachment. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes. Finally, CBGAs with the stress sensing chips were soldered to organic printed circuit board (PCB) test boards. A simulated heat sink loading applied, and the stresses were measured as a function of the clamping force. Compressive stress changes of up to − 60 MPa were observed for a 1000 N applied clamping force. The experimental test chip stress measurements were correlated with finite element simulations of the clamping process. With suitable detail in the models, excellent correlation has been obtained for the stress changes occurring during simulated heat sink clamping.

Squeezing the chip: The buildup of compressive stress in a microprocessor chip by packaging and heat sink clamping

Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials, second level CBGA solder joints, organic PCB, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high CTE ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, we have used test chips containing piezoresistive sensors to measure the buildup of mechanical stresses in a microprocessor die after various steps of the assembly process, as well as due to heat sink clamping and subsequent powered operation. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, lid attachment, CBGA assembly to PCB, and heat sink clamping). Levels exceeding 500 MPa have been observed for extremely high heat sink clamping forces. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to the high CTE ceramic chip carriers. Before packaging, the sensor resistances were measured by directly probing the individual test chip wafers. The chips were then diced, reflowed to the ceramic substrate, and then underfilled and cured. A metallic lid and second level solder balls were attached to complete the flip chip ceramic BGA components. After every packaging step (flip chip solder ball reflow, underfill dispense and cure, lid attachment and adhesive cure), the sensor resistances were re-measured, so that the die stresses induced by each assembly operation could be characterized. Finally, CBGAs with the stress sensing chips were soldered to organic PCB test boards. A simulated heat sink was then attached, and the stresses were measured as a function of the clamping force. The heat sink clamping pressure distribution was monitored using in-situ resistive sensors in the TIM2 position between the lid and heat sink. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A novel sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes and during simulated heat sink clamping.

Impact of mechanical stress on bipolar transistor current gain and Early voltage

Fundamental results for the stress dependence of the current gain and Early voltage of vertical npn and pnp bipolar junction transistors (BJTs) on (100) and (111) silicon are presented with experimental verification. These results demonstrate the direct relationship between current gain and piezoresistive coefficients and show that Early voltage is independent of stress. This information completes the data necessary for modeling the impact of stress on bipolar devices and circuits, and the modeling will facilitate simulation of the impact of process and packaging induced stress on precision analog circuits and sensors. A sample circuit simulation using the model is provided.

Understanding the impact of temperature variations on measurement of stress dependent parameters of bipolar junction transistors

The macroscopic stress dependence of bipolar junction transistors (BJTs) can be modeled by three transport model parameters as a function of stress: saturation current IS, forward current gain βF, and Early voltage VA. Recent research has shown that Early voltage VA is independent of stress, so it is not discussed in detail in this paper. Unfortunately, accurate extraction of model parameters IS and β from measurement of collector current IC and base current IB is easily compromised by the large temperature sensitivity of the BJT due to the exponential dependencies on temperature. For example, if one measures IC and IB with constant base-emitter voltage, one must contend with temperature sensitivities as large as 45 × (ΔT/T) - i. e. a 1° K change at room temperature yields a 15% change in IS, overwhelming smaller variations due to stress. Examples of these thermal errors are presented. We have developed a new non-temperature compensated approach based upon fixed emitter current biasing that still provides two degrees of freedom necessary to independently measure current gain and saturation current, but with manageable temperature sensitivity. Examples of the new measurement technique to characterize variations of β and IS are presented for vertical npn transistors under tensile and compressive stresses ranging between 0 and 150 MPa. Current gain is shown to be a quasi temperature-compensated quantity relative to either the individual collector or base currents, with the residual temperature coefficient limited by the bandgap difference between the base and emitter regions of the transistor. Our experimental results agree well with macroscopic device models based upon piezoresistivity [1] and deformation potential based formulations [2]. The stress dependent transistor models are combined with SPICE circuit simulation to demonstrate the impact of stress on basic analog IC building blocks. Measurements agree well with both theoretical and circuit simulation calculations for PTAT voltage generators, bandgap references and operational amplifier offset voltages.

Measurement of die stresses in microprocessor packaging due to thermal and power cycling

The increasingly complex packaging used in modern workstations and servers transmits a complicated set of mechanical loads to the microprocessor. Increasing die size, high CTE ceramic substrates, lead free solder joints, and ever increasing power requirements have led to increased die stress levels in packaged microprocessor die. Such stresses can degrade silicon device performance, as well as damage the copper/low-k interconnect layers, and in extreme cases, mechanical failure of the die may occur. In previous work of the authors, on-chip piezoresistive stress sensors have been utilized to quantify stress levels induced by microprocessor packaging processes such as flip chip solder joint reflow, underfill cure, and lid attachment. Good correlation has been obtained between the test chip measurements and finite element simulations of the flip chip ceramic ball grid array (FC-CBGA) component assembly process. In the current work, we have extended our past studies on the FC-CBGA microprocessor packaging configuration to investigate in-situ die stress variation during thermal and power cycling. The utilized (111) silicon sensor rosettes were able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The test chips had dimensions of 20 × 20 mm, and 3600 lead free solder interconnects (full area array) were used to connect the chips to high CTE ceramic chip carriers. A unique package carrier was developed to allow measurement of the die stresses in the FC-CBGA components under thermal and power cycling loads without inducing any additional mechanical loadings. Initial experiments consisted of measuring the die stress levels while the components were subjected to a slow (quasi-static) temperature changes from 0 to 100 C. In later testing, long term thermal cycling of selected parts was performed from 0 to 100 C (40 minute cycle, 10 minute ramps and dwells). After various durations of cycling, the sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded. From the resistance data, the stresses at each site were calculated and plotted versus time. Finally, thermal and power cycling of selected parts was performed, and in-situ measurements of the transient die stress variations were performed. Power cycling was implemented by exciting the on-chip heaters on the test chips with various power levels. During the thermal/power cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) were recorded continuously. From the resistance data, the stresses at each site were calculated and plotted versus time. The experimental test chip stress measurements were correlated with finite element simulations of power and thermal cycling events. A sequential modeling approach has been utilized to predict the build-up of die stress. The utilized method incorporates precise thermal histories of the package, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, good correlation has been obtained with the sensor data measured during thermal and power cycling.

Die stress variation in area array components subjected to accelerated life testing

Thermal cycling accelerated life testing is often used to qualify packages for various applications. Finite element life predictions for thermal cycling configurations is challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In our research, we are using test chips containing piezoresistive stress sensors to continuously characterize the in-situ die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PGA) components, ceramic ball grid array (CBGA) components, and flip chip on laminate assemblies. The utilized (111) silicon test chips are able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The die stresses are initially measured at room temperature after packaging. The assemblies are then subjected to thermal cycling from -40 to 125 C or from -55 to 125 C for up to 3000 thermal cycles. During the thermal cycling, sensor resistances at critical locations on the die device surface (e.g. die center and die corners) are recorded. From the resistance data, the stresses at each site can be calculated and plotted versus time. The experimental observations show significant cycle-to-cycle evolution in the stress magnitudes due to material aging effects, stress relaxation and creep phenomena, and development of interfacial damage. The observed stress variations as a function of thermal cycling duration are also being correlated with the observed delaminations at the die surface (as measured using scanning acoustic microscopy (C-SAM)) and finite element simulations that include material constitutive models that incorporate thermal aging effects.