Petri Eloranta

A Multimode Transmitter in 0.13

This paper presents a system-independent transmitter architecture based on a direct-digital RF-modulator which combines the D/A conversion, up-conversion, unwanted sideband rejection, power control, and part of the digital image-rejection filtering into a single mixed-signal circuit block. The multimode capability of the architecture is demonstrated with WCDMA, EDGE, and WLAN system requirements. The modulator achieves 90 dB of power control range and with an external power amplifier module, WCDMA EVM of less than 2% from signal powers of -20 dBm to +25 dBm. The noise floor level defined by the quantization noise at 190 MHz offset from the carrier is -150 dBc/Hz measured at the output of the PA with +25 dBm signal power. The analog power consumption with the maximum signal power level is 92 mW and scales down to 46 mW when reducing the signal level to -43 dBFS. The digital power consumption is 65 mW. The chip is implemented with a standard 0.13 mum 1.2 V digital CMOS with total silicon area of 4 mm2.

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An IQ-modulator constructed using direct digital-to-RF converters for wide-band multi-radio applications achieves better than -43dBc of LO-leakage and -47dBc of image rejection. The signal-level dependent maximum power consumption is 60.5mW with a -10dBm WCDMA signal. The modulator occupies 0.7mm/sup 2/ of silicon area in a standard 1.2V 0.13 /spl mu/m CMOS process.

CMOS Using Direct-Digital RF Modulator

A WCDMA transmitter based on direct-digital RF modulator has a power control range of >90dB and achieves an ACPR of -58dBc with a channel power of -2dBm. Using an external PA with a power gain of 27dB, the measured EVM is <2% with signal levels from -35 to +25dBm. The chip is fabricated in a 0.13μm 1.2V CMOS process and occupies 4mm2.

Direct-digital RF modulator IC in 0.13 /spl mu/m CMOS for wide-band multi-radio applications

The implemented ASICs, intended for mobile terminal usage, comprise a wideband high capacity OFDM direct conversion transceiver front-end for beyond 3G cellular systems. The transceiver operates with 83.2 MHz signal bandwidth and is designed for the operational frequency range of 5.15-5.725 GHz. The receiver and transmitter chips were fabricated with 0.13mum BiCMOS technology.

A WCDMA Transmitter in 0.13μm CMOS Using Direct-Digital RF Modulator

This paper presents a digital interpolation chain for non-integer variable-ratio sampling rate conversion, targeted to 4G mobile applications. Such a system is needed in all-digital transmitters, where the sampling rate of the digital input to the RF front-end must be an integer fraction of the carrier frequency. A highly configurable architecture is proposed to cope with the flexibility needed in 4G applications. The system achieves excellent ACLR of 75 dB, EVM degradation of 0.05%, and RX-band noise below -160 dBc/Hz. Digital synthesis of the circuit in a 40nm low-power CMOS process results in a core area of only 0.073 mm2. The estimated power consumption is between 6 and 29 mW, depending on channel bandwidth and transmission band.

A wideband OFDM transceiver implementation for beyond 3G radio systems

A 14-bit digitally calibrated segmented current-steering D/A-converter is presented. The 6-bit MSB-subconverter part of the DAC is formed by using two MSB arrays in parallel. The switching order of the MSB current sources is optimized with programmable mapping devices so that the current deviations of the current sources in the first array are compensated with their complementary errors in the second array. The implemented D/A-converter achieves 83.5dBc of SFDR with a 1.6MHz, -0.5dBFS signal and a clock rate of 100Msamples/s. With -0.3dBFS signal swing the calibrated DNL and INL are 0.9LSB and 1.5LSB, respectively. The DAC consumes less than 60mW at 1.2/2.5V power supply with the sample rate of 100MSPS. The silicon area of the DAC is 0.65mm2. The chip was fabricated in 0.13mum CMOS process

A configurable sampling rate converter for all-digital 4G transmitters

This paper presents a digital interpolation chain for non-integer large-ratio sampling rate conversion, targeted to 4G applications. Such a system is needed in all-digital transmitters, where the sampling rate of the digital input to the RF front-end must be an exact submultiple of the carrier frequency. A highly flexible architecture is proposed to reduce system complexity when the RF requirements are more relaxed. The presented interpolation chain has been especially optimized by taking into account the requirements for LTE and LTE-A, but it can be used in multistandard applications as well. The system achieves excellent ACLR of 83 dB, EVM degradation of 0.03%, and RX-band noise below -160 dBc/Hz.