Sandeepan DasGupta

Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs

A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100-nm SRAM memory cells can be upset by a critical charge (Qcrit) of 1.1 fC or less, they may exhibit significantly higher upset rates than those reported in earlier technologies. Because of this, single-bit-correcting ECCs may become impractical due to memory scrubbing rate limitations. The overhead needed for protecting memories with a triple-bit-correcting ECC is examined relative to an approximate 2X ldquoprocess generationrdquo scaling penalty in area, speed, and power.

Analysis of Parasitic PNP Bipolar Transistor Mitigation Using Well Contacts in 130 nm and 90 nm CMOS Technology

Three-dimensional TCAD models are used in mixed- mode simulations to analyze the effectiveness of well contacts at mitigating parasitic PNP bipolar conduction due to a direct hit ion strike. 130 nm and 90 nm technology are simulated. Results show careful well contact design can improve mitigation. However, well contact effectiveness is seen to decrease from the 130 nm to the 90 nm simulations.

Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM

Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upsetting the logic state of memory circuits. In this paper the authors investigate the critical charge (Qcrit) required to upset a 6T SRAM cell designed in a commercial 90nm process. The authors characterize Qcrit using different current models and show that there are significant differences in Qcrit values depending on which models are used. Discrepancies in critical charge characterization are shown to result in under-predictions of the SRAMs associated soft error rate as large as two orders of magnitude. For accurate Qcrit calculation, it is critical that 3D device simulation is used to calibrate the current pulse modeling heavy ion strikes on the circuit, since the stimuli characteristics are technology feature size dependant. Current models with very fast characteristic timing parameters are shown to result in conservative soft error rate predictions; and can assertively be used to model ion strikes when 3D simulation data is not available.

Directional Sensitivity of Single Event Upsets in 90 nm CMOS Due to Charge Sharing

Heavy-ion testing of a radiation-hardened-by-design (RHBD) 90 nm dual interlocked cell (DICE latch) shows significant directional sensitivity results impacting observed cross-section and LET thresholds. 3-D TCAD simulations show this directional effect is due to charge sharing and parasitic bipolar effects due to n-well potential collapse.

Effect of Well and Substrate Potential Modulation on Single Event Pulse Shape in Deep Submicron CMOS

Simulations are used to characterize the single event transient current and voltage waveforms in deep submicron CMOS integrated circuits. Results indicate that the mechanism controlling the height and duration of the observed current plateau is the redistribution of the electrostatic potential in the substrate following a particle strike. Quantitative circuit and technology factors influencing the mechanism include restoring current, device sizing, and well and substrate doping.

Design Techniques to Reduce SET Pulse Widths in Deep-Submicron Combinational Logic

Analysis of 90 nm CMOS SET response quantifies the interaction between charge collection and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET pulse width difference between an n-hit and p-hit is due to parasitic bipolar amplification on the PMOS device. This difference is exploited to optimize transistor sizing and n-well contact layout for SET RHBD in combinational logic.

Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology

This work presents an efficient hybrid simulation approach, developed for accurate characterization of single-event transients (SETs) in combinational logic. Using this approach, we show that charges as small as 3.5fC can introduce transients in commercial 90nm CMOS technology, hence increasing the likelihood of SET-induced soft errors. SET pulse-widths as large as 942ps are predicted at an LET (Linear Energy Transfer) of 60MeV-cm2/mg. Process-corner variations are shown to modulate SET pulse-widths by up-to 75%. The results suggest that selection of mitigation techniques for SET radiation-hardened circuits cannot exclusively rely on baseline process analyses, as they might grossly underestimate the true SET risk to the design.

Novel Energy-Dependent Effects Revealed in GeV Heavy-Ion-Induced Transient Measurements of Antimony-Based III-V HEMTs

High-bandwidth (16 GHz) time-resolved charge-collection measurements for heavy-ion irradiation of up to 70 GeV/amu are performed on low-power 6.1 Å lattice spacing InAlSb/InAs HEMT devices. Event cross sections are measured to be significantly larger than the active areas of the devices. Novel energy-dependent effects are observed.

1/f Noise in GaN HEMTs grown under Ga-rich, N-rich, and NH3-rich conditions

Abstract The magnitude of the low-frequency 1/f noise in GaN/AlGaN HEMTs grown under Ga-rich, N-rich, and NH3-rich conditions varies in response to hot-electron stress. Density-functional-theory (DFT) calculations show that the Ga vacancies that are responsible for the positive shift in pinch-off voltage due to electrical stress in Ga-rich and N-rich devices do not contribute significantly to the observed changes in 1/f noise with electrical stress. The N anti-sites that cause negative shifts in pinch-off voltage in ammonia-rich devices can cause an increase in the noise magnitude after stress. DFT calculations also show that singly hydrogenated and dehydrogenated Ga–N divacancies also can contribute to the noise before and after stress, respectively. A decrease in noise magnitude is also observed in some devices after stress.

Single Event Transient (SET) Response of National Semiconductor's ELDRS-Free LM139 Quad Comparator

Heavy ion and pulsed laser Single Event Transient (SET) data are presented for National Semiconductors LM139AxLQMLV (5692R9673802VxA). The SET signatures for this part are compared to older versions of the part. The results confirm complications in performing SET testing on bipolar analog products reported by others plus raise new considerations when evaluating SET test results.