Oluwole A. Amusan

Charge Collection and Charge Sharing in a 130 nm CMOS Technology

Charge sharing between adjacent devices can lead to increased Single Event Upset (SEU) vulnerability. Key parameters affecting charge sharing are examined, and relative collected charge at the hit node and adjacent nodes are quantified. Results show that for a twin-well CMOS process, PMOS charge sharing can be effectively mitigated with the use of contacted guard-ring, whereas a combination of contacted guard-ring, nodal separation, and interdigitation is required to mitigate the NMOS charge sharing effect for the technology studied

Characterization of Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS Technologies

The distributions of SET pulse-widths produced by heavy ions in 130-nm and 90-nm CMOS technologies are measured experimentally using an autonomous pulse characterization technique. The event cross section is the highest for SET pulses between 400 ps to 700 ps in the 130-nm process, while it is dominated by SET pulses in the range of 500 ps to 900 ps in the 90-nm process. The increasing probability of longer SET pulses with scaling is a key factor determining combinational logic soft errors in advanced technologies. Mixed mode 3D-TCAD simulations demonstrate that the variation of pulse-width results from the variation in strike location.

A Bias-Dependent Single-Event Compact Model Implemented Into BSIM4 and a 90 nm CMOS Process Design Kit

A single-event model capable of capturing bias- dependent effects has been developed and integrated into the BSIM4 transistor model and a 90 nm CMOS process design kit. Simulation comparisons with mixed mode TCAD are presented.

Analysis of Parasitic PNP Bipolar Transistor Mitigation Using Well Contacts in 130 nm and 90 nm CMOS Technology

Three-dimensional TCAD models are used in mixed- mode simulations to analyze the effectiveness of well contacts at mitigating parasitic PNP bipolar conduction due to a direct hit ion strike. 130 nm and 90 nm technology are simulated. Results show careful well contact design can improve mitigation. However, well contact effectiveness is seen to decrease from the 130 nm to the 90 nm simulations.

Single Event Upsets in Deep-Submicrometer Technologies Due to Charge Sharing

Circuit and 3D technology computer aided design mixed-mode simulations show that the single event upset vulnerability of 130- and 90-nm hardened latches to low linear energy transfer (LET) particles is due to charge sharing between multiple nodes as a result of a single ion strike. The low LET vulnerability of the hardened latches is verified experimentally.

Directional Sensitivity of Single Event Upsets in 90 nm CMOS Due to Charge Sharing

Heavy-ion testing of a radiation-hardened-by-design (RHBD) 90 nm dual interlocked cell (DICE latch) shows significant directional sensitivity results impacting observed cross-section and LET thresholds. 3-D TCAD simulations show this directional effect is due to charge sharing and parasitic bipolar effects due to n-well potential collapse.

Effect of Well and Substrate Potential Modulation on Single Event Pulse Shape in Deep Submicron CMOS

Simulations are used to characterize the single event transient current and voltage waveforms in deep submicron CMOS integrated circuits. Results indicate that the mechanism controlling the height and duration of the observed current plateau is the redistribution of the electrostatic potential in the substrate following a particle strike. Quantitative circuit and technology factors influencing the mechanism include restoring current, device sizing, and well and substrate doping.

Design Techniques to Reduce SET Pulse Widths in Deep-Submicron Combinational Logic

Analysis of 90 nm CMOS SET response quantifies the interaction between charge collection and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET pulse width difference between an n-hit and p-hit is due to parasitic bipolar amplification on the PMOS device. This difference is exploited to optimize transistor sizing and n-well contact layout for SET RHBD in combinational logic.

Propagating SET Characterization Technique for Digital CMOS Libraries

A circuit architecture based on simple logic gates is described which uses small chip areas and low speed testing to characterize single event transients for digital applications. Utility of this architecture is demonstrated with heavy ion data on a 130 nm library

Mitigation Techniques for Single-Event-Induced Charge Sharing in a 90-nm Bulk CMOS Process

In this paper, mitigation techniques to reduce the increased SEU cross section associated with charge sharing in a 90-nm dual-interlocked-cell latch are proposed. The increased error cross section is caused by heavy-ion angular strikes depending on the direction of the ion strike, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal spacing as a mitigation technique shows an order of magnitude decrease on upset cross section as compared to a conventional layout, and the use of guard-rings show no noticeable effect on upset cross section.