Sang-hoon Ahn

Reliable integration of robust porous ultra low-k (ULK) for the advanced BEOL interconnect

In order to address the increasing RC and reliability challenges at the advanced technology nodes, a new robust ULK was developed that incorporates the bridging carbon atoms (Si-[CH2]x-Si) in p-SiOCH matrix. Its elastic modulus and plasma damage resistance were improved more than 40% at the same dielectric constant than the commercially available ULK. These improvements are attributed to 80% higher atoms that exist in both Si-[CH2]x-Si and Si-CH3 structures with its pore size 23% smaller. Furthermore, its superb properties resulted in 3~4% capacitance reduction, and improvement of TDDB and EM TTF (time to failure) by 2 order and 2~3 times, respectively, on an advanced BEOL vehicle.

Robust porous SiOCH (k=2.5) for 28nm and beyond technology node

Robust p-SiOCH was deposited in a PECVD reactor using Si precursor with Si-C-C-Si bond structure. It achieved its elastic modulus of 8.4GPa at k=2.55, comparable to the reference silica-based p-SiOCH that has been widely evaluated among the major chipmakers. However, its post-integration k increase was ∼0.1 on a 100nm-pitched single damascene line and negligible on a 90nm-pitched trench first metal hardmask dual damascene line. Its superb performance in plasma damage resistance without the sacrifice in its mechanical strength can be attributed to the presence of bridged carbon(s) between Si atoms in addition to the methyl functional group. According to 29Si and 13C nuclear magnetic resonance (NMR) spectra, bridged carbon and carbon in the methyl group exist approximately in 1∶1 ratio in the robust p-SiOCH.

Successful recovery of moisture-induced TDDB degradation for Cu/ULK(k=2.5) BEOL interconnect

Cu/ULK(k=2.5) dual Damascene back end of line(BEOL) dielectric degradation was studied with respect to post Cu CMP delay prior to dielectric diffusion barrier deposition. The threshold of the delay time was observed beyond which line-to-line leakage current increased rapidly while the dielectric breakdown voltage decreased. This air exposure-dependent degradation was attributed to moisture absorption by damaged ULK during integration, and caused premature TDDB (time-dependent dielectric breakdown) failure. It was found that combination of moisture removal by damage-free UV and mild plasma treatment was able to restore dielectric breakdown voltage as well as TDDB time to failure even well past the threshold of delay time.

High performance Cu/low-k interconnect strategy beyond 10nm logic technology

CVD-Ru based reflow Cu scheme demonstrates robust gap fill performance at 10nm and 7nm node equivalent patterns. Potential EM and TDDB reliability concerns associated with Ru CMP are identified and successfully addressed by the application of new processes and materials. This suggests our proposed scheme can be one of promising candidates for 10nm node logic device and beyond.