Sang-don Nam

Highly scalable on-axis confined cell structure for high density PRAM beyond 256Mb

We firstly fabricated on-axis confined structure and evaluated based on 64Mb PRAM with 0.12/spl mu/m-CMOS technologies. Ge/sub 2/Sb/sub 2/Te /sub 5/ was confined within small pore, which resulted in low writing current of 0.4mA. The pore is on-axis with upper and lower contacts, which leads to good scalability of PRAM above 256Mb. The confined structure was relatively insensitive to small cell edge damage effect. The on-axis confined structure is a promising candidate for high density PRAM due to low writing current, good scalability, and insensitiveness to edge damage.

Enhanced Retention Characteristics of Pb(Zr, Ti)O3 Capacitors by Ozone Treatment

Effects of ozone treatment and charged defects on retention characteristics of Ir/IrO2/Pb(Zr, Ti)O3 (PZT)/Pt/IrO2/Ir capacitors were systematically investigated. For these purposes, PZT thin films were exposed to ozone environment to promote enhanced surface oxidation. After baking the Ir/IrO2/PZT/Pt/IrO2/Ir capacitors at 125°C for 500 h, degradation of Qnv (non-volatile charge) value of the ozone-treated capacitors was approximately 17.6%, that is less than one fifth of that of the untreated capacitors. X-ray photoelectron spectroscopy (XPS) and Auger electron spectroscopy (AES) studies showed that the amount of oxygen-vacancies near the PZT surface was dramatically decreased by the ozone treatment. The Schottky barrier height of the ozone-treated capacitors increased when compared to that of the untreated capacitors (the Schottky barrier height of the untreated and the ozone-treated capacitor was 0.29 eV and 0.43 eV, respectively). Therefore, one can conclude that the retention characteristics seem to be closely associated with oxygen related defects near the ferroelectric/electrode interface and the control of the interface properties of PZT thin film is a key technology to pursue reliable function characteristics of ferroelectric random access memory (FRAM) devices.

Highly reliable 0.15 μm/14 F2 cell ferroelectric random access memory capacitor using SrRuO3 buffer layer

We investigated a novel technique of modifying the interface between a Pb(ZrxTi1-x)O3 (PZT) thin film and electrodes for high density 64 Mbit ferroelectric random access memory (FRAM) device. Using a SrRuO3 buffer layer, we successfully developed highly reliable 0.15 µm/14 F2 cell FRAM capacitors with 75-nm-thick polycrystalline PZT thin films. The SrRuO3 buffer layer greatly enhanced ferroelectric characteristics due to the decrease in interfacial defect density. In PZT capacitors with a total thickness of 180 nm for whole capacitor stack, a remnant polarization of approximately 42 µC/cm2 was measured with a 1.4 V operation. In addition, an opposite state remnant polarization loss of less than 15% was observed after baking at 150 °C for 100 h. In particular, we found that the SrRuO3 buffer layer also played a key role in inhibiting the diffusion of Pb and O from the PZT thin films.

Electrical Properties of Crystalline Ta2O5 with Ru Electrode

As one candidate capacitor for dynamic random access memories (DRAMs) of 4 Gbit and beyond, we investigated the electrical properties of Ru/Ta2O5/Ru. In this paper, the dielectric constant of Ta2O5 was measured as a function of annealing temperature and, also, its dependence on film thickness was studied. The effect of postannealing, which was performed after forming a capacitor, on the leakage current of Ru/crystalline-Ta2O5/Ru capacitor was evaluated. Additionally, the leakage current was investigated as a function of Ta2O5 film thickness. Through these experiments, a reliable 7 A Toxeq. of Ta2O5 with a Ru electrode was obtained, which indicates that the Ru/crystalline-Ta2O5/Ru capacitor is a promising candidate for DRAMs of 4 Gbit and beyond.

Novel integration technologies for highly manufacturable 32 Mb FRAM

Ferroelectric random access memory (FRAM) has been considered as a future memory device due to its ideal properties such as non-volatility, high endurance, fast write/read time and low power consumption. Recently, a 4 Mb FRAM was developed using 1T1C capacitor-on-bit-line (COB) cell structure and triple metallization (S.Y. Lee et al, VLSI Symp. Tech. Dig., p. 141, 1999). However, the current 4 Mb FRAM device cannot satisfactorily be used as a major memory device for stand-alone application due to its low density, cost ineffectiveness, and large cell size factor. Therefore, it is strongly desired to develop high density FRAM devices beyond 32 Mb for application to stand-alone memory devices. In this paper, we report for the first time development of a highly manufacturable 32 Mb FRAM, achieved by 300 nm capacitor stack technology in a COB cell structure, a double encapsulated barrier layer (EBL) scheme, an optimal inter-layer dielectric (ILD) and intermetallic dielectric (IMD) technology, and a novel common cell-via scheme.

Integration of ferroelectric random access memory devices with Ir/IrO2/Pb(ZrxTi1-x)O3/Ir capacitors formed by metalorganic chemical vapor deposition-grown Pb(ZrxTi1-x)O3

Metal organic chemical vapor deposition (MOCVD) of Pb(ZrxTi1-x)O3 (PZT) and its capacitor module process were established for ferroelectric memory device integration. The 130 nm-thick PZT films were deposited on Ir layers at 530°C or 550°C. The remnant polarization of the Ir/IrO2/PZT/Ir capacitors is in the range of 15 to 21 µC/cm2, and their leakage current is 10-5 A/cm2 at 2.5 V without additional annealing. The degradation in their switching endurance is less than 5% after 1010 cycles, indicating that the interfaces formed between the PZT and Ir layers can be optimized to improve their fatigue properties. To evaluate the capacitors on the devices, the conventional backend process was performed after encapsulating the capacitors with AlOx/TiOx layers located on the poly-Si plug. High charge separation and fully functional bit activities were obtained, demonstrating that this MOCVD-PZT process is a reliable integration scheme for high-density ferroelectric memory devices.

Highly reliable Cu interconnect strategy for 10nm node logic technology and beyond

CVD-Ru represents a critically important class of materials for BEOL interconnects that provides Cu reflow capability. The results reported here include superior gap-fill performance, a solution for plausible integration issues, and robust EM / TDDB properties of CVD-Ru / Cu reflow scheme, by iterative optimization of process parameters, understanding of associated Cu void generation mechanism, and reliability failure analysis, thereby demonstrating SRAM operation at 10 nm node logic device and suggesting its use for future BEOL interconnect scheme.

Superior Cu fill with highly reliable Cu/ULK integration for 10nm node and beyond

It is possible to overcome Cu void issues beyond 10nm node device by adapting CVD-Ru liner instead of conventional PVD Ta liner. However, CVD Ru liner integration degrades TDDB performance without optimizing its scheme. In this paper, superior gap-fill performance without TDDB performance degradation will be described in our optimized integration scheme along with a proposal for the mechanism of TDDB degradation in the Ru integration scheme. CVD-Ru liner is the prime candidate for Cu metallization at 10nm node and beyond.

Plasma-assisted dry etching of ferroelectric capacitor modules and application to a 32M ferroelectric random access memory devices with submicron feature sizes

In the manufacturing of a 32M ferroelectric random access memory (FRAM) device on the basis of 0.25 design rule (D/R), one of the most difficult processes is to pattern a submicron capacitor module while retaining good ferroelectric properties. In this paper, we report the ferroelectric property of patterned submicron capacitor modules with a stack height of 380 nm, where the 100 nm-thick Pb(Zr, Ti)O3 (PZT) films were prepared by the sol-gel method. After patterning, overall sidewall slope was approximately 70° and cell-to-cell node separation was made to be 80 nm to prevent possible twin-bit failure in the device. Finally, several heat treatment conditions were investigated to retain the ferroelectric property of the patterned capacitor. It was found that rapid thermal processing (RTP) treatment yields better properties than conventional furnace annealing. This result is directly related to the near-surface chemistry of the PZT films, as confirmed by X-ray photoelectron spectroscopy (XPS) analysis. The resultant switching polarization value of the submicron capacitor was approximately 30 µC/cm2 measured at 3 V.

Robust porous SiOCH (k=2.5) for 28nm and beyond technology node

Robust p-SiOCH was deposited in a PECVD reactor using Si precursor with Si-C-C-Si bond structure. It achieved its elastic modulus of 8.4GPa at k=2.55, comparable to the reference silica-based p-SiOCH that has been widely evaluated among the major chipmakers. However, its post-integration k increase was ∼0.1 on a 100nm-pitched single damascene line and negligible on a 90nm-pitched trench first metal hardmask dual damascene line. Its superb performance in plasma damage resistance without the sacrifice in its mechanical strength can be attributed to the presence of bridged carbon(s) between Si atoms in addition to the methyl functional group. According to 29Si and 13C nuclear magnetic resonance (NMR) spectra, bridged carbon and carbon in the methyl group exist approximately in 1∶1 ratio in the robust p-SiOCH.