Sang-Jin Hyun

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.

Chemically Homogeneous and Thermally Robust Ni1–xPtxSi Film Formed Under a Non-Equilibrium Melting/Quenching Condition

To synthesize a thermally robust Ni1-xPtxSi film suitable for ultrashallow junctions in advanced metal-oxide-semiconductor field-effect transistors, we used a continuous laser beam to carry out millisecond annealing (MSA) on a preformed Ni-rich silicide film at a local surface temperature above 1000 °C while heating the substrate to initiate a phase transition. The melting and quenching process by this unique high-temperature MSA process formed a Ni1-xPtxSi film with homogeneous Pt distribution across the entire film thickness. After additional substantial thermal treatment up to 800 °C, the noble Ni1-xPtxSi film maintained a low-resistive phase without agglomeration and even exhibited interface flattening with the underlying Si substrate.

Improvement of Performance and Data Retention Characteristics of Sub-50nm DRAM by HfSiON Gate Dielectric

For the first time, we have successfully integrated HfSiON gate dielectric to DRAM and obtained excellent data retention time. Lower gate leakage current and better mobility of HfSiON than plasma nitrided oxide resulted in a 22% smaller propagation delay measured at CMOS inverter as well as one order of magnitude lower stand-by current for DRAM. Optimized gate poly-Si reoxidation and high Vt of HfSiON cell Tr increased DRAM data retention time as much as 2 times longer than plasma nitrided oxide. We demonstrated that HfSiON could enhance performance and be beneficial to date retention time of high thermal budget DRAM at the same time.

Gate oxide effect on wafer level reliability of next generation dram transistors

Wafer level reliability (WLR) issues of DRAM cell and peripheral transistors are discussed. Since the 70 nm technology node, recessed transistors have been accepted for assuring data retention time of DRAM cell transistors. Various recessed transistor structures suggest that the most important issue in reliability, in addition to optimizing data retention time, is the elimination of local regions of concentrated electric fields. In this paper, by modulating the cell gate oxidation process, local field concentration is effectively reduced. Particularly, the introduction of a radical oxidation process can create cell transistors that are more immune to Fowler-Nordheim (F-N) stress, which can degrade interface quality during cell transistor operation. On the other had, for DRAM peripheral transistors, for DRAM peripheral transistors, which currently use dual poly-Si gates and SiON dielectrics, high-k/metal gate (HK/MG) structure are expected to be adopted at the 20 nm technology node for improved equivalent oxide thickness (EOT) scaling. The high thermal budget of a conventional DRAM manufacturing process can significantly impact HK/MG WLR issues. However, we have evaluated reliability characteristics for HK/MG WLR on DRAM cell and peripheral devices, and concluded that WLR issues will not be critical for operation.