Yu-gyun Shin

Ultrathin gate oxide with a reduced transition layer grown by plasma-assisted oxidation

Ultrathin SiO2 grown by plasma-assisted oxidation (plasma oxide) has been investigated by high-resolution x-ray photoemission spectroscopy and medium energy ion scattering spectroscopy. We found that the plasma oxide grown at the low temperature of 400°C has a thinner transition layer than conventional thermal oxide. This thinner transition layer in the plasma oxide not only decreased the gate leakage current effectively, but also enhanced the reliability of the gate oxide. We attribute these electrical properties of the plasma oxide to the reduction of the transition layer.

A highly manufacturable low-k ALD-SiBN process for 60nm NAND flash devices and beyond

For the first time, low-k dielectric ALD-SiBN (atomic layer deposition) is successfully developed and applied on poly-Si/WSix gate as a spacer for reduction of parasitic capacitance between the cells. ALD-SiBN deposition is performed at 630/spl deg/C using dichlorosilane (SiH/sub 2/Cl/sub 2/-DCS), boron-trichloride (BCl/sub 3/) and ammonia (NH/sub 3/) as precursors. Compared with the conventional silicon nitride, ALD-SiBN exhibits similar film properties at lower dielectric constant. ALD-SiBN layer is deposited on poly-Si/WSix stack gate in 90nm NAND flash device. A significant reduction (>15%) of the floating-gate coupling voltage is achieved by employing SiBN compared with SiN spacer. In addition, excellent data retention characteristics (@HTS) is identified by applying low-k dielectric SiBN layer as a spacer on 90nm NAND flash device.

Performance Boosting of Peripheral Transistor for High Density 4Gb DRAM Technologies by SiGe Selective Epitaxial Growth Technique

The SiGe SD structure in peripheral PMOS area of DRAM was successfully integrated without any degradation of peripheral NMOS properties, which is the first approach to DRAM. The PMOS performance enhancement was found to be more than 40%. The authors suggest the SiGe SD structure as the key solution for the improvement of peripheral PMOS transistor properties in sub-50nm DRAM technology

Ultrashallow Arsenic n+/p Junction Formed by AsH3 Plasma Doping

We have investigated the ultrashallow n+/p junction formed by AsH3 plasma doping (PLAD) and the effect of hydrogen on dopant activation. Since hydrogen balance gas (99% H2) was used for AsH3 PLAD, the incorporation of a significant concentration of hydrogen resulted after PLAD. The incorporated hydrogen caused various problems, such as low dopant activation, high resistance, and high leakage current. These problems were traced to hydrogen-induced damage, which was confirmed by cross-sectional transmission electron microscopy (XTEM). Therefore, pre-annealing at low temperature, which can effectively reduce the undesired hydrogen effects, is a necessary step toward obtaining a high-quality, ultrashallow arsenic n+/p junction via AsH3 PLAD.

Effects of plasma nitridation on the electrical properties of nitrided oxide gate dielectric for DRAM application

We reduced the gate tunneling current by seven times and suppressed NBTI using plasma nitridation-induced re-oxidation (PIROX). In plasma nitrided gate oxynitride, the nitrogen concentration at the MOS interface is determined after plasma nitridation process, which affects the electrical and physical properties of gate oxynitride. To facilitate the control of nitrogen concentration at the MOS interface, an additional re-oxidation process is needed, but decreasing the nitrogen concentration. In this paper, the plasma nitridation process is proposed that realizes simultaneously the nitridation and re-oxidation without an additional process and the decrease of nitrogen concentration. The control of nitrogen concentration and the amount of re-oxidation under high pressure process improves the gate tunneling current, mobility, and NBTI.

Hole trap effect on time-dependent-dielectric breakdown (TDDB) of high-voltage peripheral nMOSFETs in flash memory application

In this work, the TDDB mechanism in high-voltage nMOSFETs with high-density of pre-existing defects in the gate oxide is investigated. In contrast to the traditional nMOSFETs with very few defects in the gate oxide, the additional hole trapping through the stress-induced generated defects close to the gate side not only induce longer fail time, but also induce smaller voltage acceleration factor and lower 10-year Vmax.

Electrical Characteristics of Ultrashallow p + ∕ n Junction Formed by BF3 Plasma Doping and Two-Step Annealing Process

We have investigated ultrashallow p + /n junctions formed by BF 3 plasma doping. Conventional one-step annealing processes such as rapid thermal annealing or excimer laser annealing (ELA) are not effective methods for high activation of boron. Furthermore, it is known that fluorine can retard dopant activation. In order to reduce fluorine concentration, we propose additional preannealing at 600°C for 10 min followed by ELA. This process dramatically improved the boron activation ratio, while maintaining the same junction depth. The improvement of dopant activation is attributed to significant out-diffusion of fluorine which in turn enhances activation of boron during ELA.

Ultrashallow p+/n junction prepared by low energy BF3 plasma doping and KrF excimer laser annealing

We have investigated the activation and deactivation of the 1 kV BE 3 plasma doping (PLAD) with excimer laser annealing (ELA). Half of the dopants were activated by ELA, and the deactivation was dramatically increased after the postannealing. We have confirmed that 1 kV BE 3 PLAD did not form an amorphous layer at the substrate using X-ray transmission electron microscopy (X-TEM) and that boron and fluorine segregated after annealing using secondary ion mass spectroscopy profiles and plane-view TEM. Based on the results, we proved that fluorine can suppress boron diffusion, although it retards the activation and increases the deactivation of BE 3 PLAD with ELA.

The P-SOG filling Shallow Trench Isolation technology for sub-70 nm device

A novel Polysilazane-based inorganic Spin-On-Glass filling Shallow Trench Isolation (P-SOG filling STI) technology is developed for sub-70 nm devices, for the first time. A key processing step of this P-SOG filling STI technology is annealing after a CMP process. The post-CMP P-SOG annealing eliminates a field oxide recess problem. This technology shows good electrical characteristics compared with a HDP oxide filling STI. The P-SOG filling STI is a promising candidate for the future isolation technology.