Hong-bae Park

A Novel DRAM Cell Transistor Featuring a Partially-insulated Bulk FinFET (Pi-FinFET) with a pad-Polysilicon Side Contacts (PSC)

The pad-polysilicon side contact (PSC) has drastically improved the performance of the partially-insulated bulk FinFET (Pi-FinFET). PSC enabled to dope a source and drain (S/D) of the fin structure uniformly from the top of the fin to the Pi layer. Since the uniform S/D increases effective channel width, the drivability was increased by 100% compared to the conventional bulk FinFET cell. Nevertheless, hot carrier (HC) lifetime was extended because the position of the highest electric field was nearer to the gate edge compared to the conventional. The total junction leakage current became 50% of the conventional due to the Pi layer. Undoped silicon selective epitaxial growth (SEG) buffered PSC could control gate induced drain leakage (GIDL) to the same level of conventional bulk FinFET. In addition, by optimizing fin height, 25% less word line capacitance (Cwl) was achieved. We place this Pi-FinFET with PSC is one of the promising candidates for the future FinFET DRAM cell technology.

Front-end-of-line (FEOL) optimization for high-performance, high-reliable strained-Si MOSFETs; from virtual substrate to gate oxidation

Front-end-of-line (FEOL) process parameters including virtual substrate (Si/Si/sub 1-x/Ge/sub x/), shallow-trench-isolation (STI) process, and gate oxidation have strong effects on performance and reliability of strained-Si MOSFETs such as gate oxide integrity (GOI), threshold voltage (V/sub TH/ roll-off, reliability behavior including junction breakdown and device isolation characteristics. It is found that gate oxide integrity can be improved by 1 order of magnitude by applying low-temperature, plasma oxidation process as compared with thermal oxidation, junction leakage and device isolation characteristics can be improved by 1 order of magnitude and by two times, respectively, by using low-defect virtual substrate and further defect-curing process, and parameters related with STI process such as thin SiN layer and oxide densification temperature must be optimized both to reduce junction leakage current and to improve device performance such as Ion-Ioff characteristics.