Il-Yong Park

BD180 - a new 0.18 μm BCD (Bipolar-CMOS-DMOS) Technology from 7V to 60V

We present a new BCD technology in a 0.18 μm technology platforms with a capability of 7 to 60V high-voltage devices such as DEMOS and LDMOS. The developed 0.18 mum BCD process provides various kinds of high voltage LDMOS such as 7, 12, 20, 50, 60 V LDMOS transistors for variety of applications. The power LDMOS transistors in the process have very competitive specific on-resistance compared to previous results.

A novel technique for fabricating high reliable trench DMOSFETs using self-align technique and hydrogen annealing

A novel technique for fabricating high reliability trench DMOSFETs using three mask layers is realized to obtain cost-effective production capability, higher cell density and current driving capability, and higher reliability. This technique provides a unit cell with 2.3/spl sim/2.4 /spl mu/m pitch and a channel density of 100 Mcell/in/sup 2/. Specific on-resistance is 0.36 m/spl Omega//spl middot/cm/sup 2/ with a blocking voltage of 43 V at a gate voltage of 10 V and 5 A source-to-drain current. The time to breakdown of gate oxide grown on the hydrogen annealed trench surface is much longer than that of oxide grown on a nonhydrogen annealed trench surface.

Implementation of buffered Super-Junction LDMOS in a 0.18um BCD process

We experimentally demonstrate a Super-Junction LDMOS transistor in a 0.18 µm BCD technology. The buffered Super-Junction structure is implemented by the use of existing N- and P-drift layer, which are optimized for conventional 20V to 30V LDMOS transistors. The breakdown voltage and the specific on-resistance of the fabricated Super-Junction LDMOS are 98.6 V and 1.01 mΩ⋅cm2, respectively. The TLP measurement results show fairly good electrical SOA characteristics up to 78V for all gate voltages.

BCD (Bipolar-CMOS-DMOS) technology trends for power management IC

This paper reviews the technology trends of BCD (Bipolar-CMOS-DMOS) technology in terms of voltage capability, switching speed of power transistor, and high integration of logic CMOS for SoC (System-on-Chip) solution requiring high-voltage devices. Recent trends such like modularity of the process, power metal routing, and high-density NVM (Non-Volatile Memory) are also discussed.

Implementation of low Vgs (1.8V) 12V RF-LDMOS for high-frequency DC-DC converter applications

A 12V low Vgs (1.8V) RF-N/PLDMOS have been successfully implemented on the 0.18 μm analog CMOS process without thermal budget addition. N- and P-ch LDMOS needs additional body and drift implants, respectively. A short channel length and a small overlap of gate-to-drain were accomplished by the optimization of implant conditions for the source halo and the drift region which is followed by the gate formation with 30 Å gate oxide. Cut-off frequency 37.2GHz and 12.9GHz each for NLDMOS and PLDMOS were achieved with breakdown voltage of 20V. The long-term wafer level HCI test result showed Idlin shift under 10% after 150Ksec stress at Vds=12V and Vgs=1.8V.

A versatile 30V analog CMOS process in a 0.18μm technology for power management application

A versatile 30V analog CMOS process in a 0.18 μm technology node has been developed by using cost-effective and modular fashion. To reduce the thermal budget deep NWELL isolation is formed after CMOS well formation. The drain-extended (DE) CMOS from 7V to 30V shows very competitive trade-off performance between the breakdown voltage and the specific on-resistance. In addition, low 1/f noise of 5V CMOS can be obtained by pure gate oxide process.

Novel process techniques for fabricating high density trench MOSFETs with self-aligned N/sup +//P/sup +/ source formed on the trench side wall

Novel process techniques for fabricating highly dense trench MOSFETs are proposed and verified by experimental and numerical results. P/sup +/ region for p-base contact and N/sup +/ source are formed on the trench side wall by using self-aligned process techniques including triple trench etching. Two-dimensional process and device simulation is performed by using SILVACO with the cell pitch of 1.0 /spl mu/m for the proposed trench MOSFET. The simulated breakdown voltage and on-resistance are 45 V and 12.9 m/spl Omega/-mm/sup 2/, respectively.

Implementation of 85V High Side LDMOS with n-layer in a 0.35um BCD Process

This paper report 85 V high-side LDMOS which is implemented in a conventional 0.3 5 um BCDMOS process using one additional mask. The process has no thermal budget modification but use simple additional implant step. Also it is completely compatible with the conventional BCDMOS process and has similar performances with 80 V SOI LDMOS.

Highly reliable LDMOSFETs employing uneven racetrack sources for PDP driver applications

The electrical characteristics of n-LDMOSFETs with uneven racetrack source (URS) and conventional racetrack source (CRS) before and after electrical DC stress were investigated to improve hot carrier immunity for PDP driver. The breakdown voltage of n-LDMOSFET with URS is improved by 15% as compared to that of n-LDMOSFET with CRS at on-state. The decrease of threshold voltage (V/sub t/) and maximum transconductance (g/sub mmax/) of n-LDMOSFET with URS after electrical DC stress are about 10 times lower than those of n-LDMOSFET with CRS. The variation of specific on-resistance (R/sub on/) of n-LDMOSFET with URS after DC stress is much lower than that of n-LDMOSFET with CRS.

Highly reliable p-LDMOSFET with an uneven racetrack source for PDP driver IC applications

The electrical characteristics of p-LDMOSFETs with uneven racetrack source (URS) and conventional racetrack source (CRS) before and after electrical DC stress were investigated to improve hot carrier immunity for PDP driver. The breakdown voltage of p-LDMOSFET with URS in on-state was about 30% higher than that of p-LDMOSFET with CRS at on-state. The variations of threshold voltage (V/sub t/), maximum transconductance (g/sub mmax/), saturated drain current (I/sub DSsat/) of p-LDMOSFET with URS after electrical DC stress were much lower than those of p-LDMOSFET with CRS. The variation of specific-on resistance (R/sub on/) of p-LDMOSFET with URS after stress was much lower than that of p-LDMOSFET with CRS.