Sanghoon Kang

A multistandard multiband mobile TV RF SoC in 65nm CMOS

The mobile TV applications such as DVH-H/T, T-DMB/DAB, ISDB-T are recently emerging all over the world. To support various applications, the multistandard and multiband mobile TV RF tuner is developed as a cost-effective and size-effective solution [1]. The demand for smaller form factor and power consumption reduction of RF and Channel is very high, and SoC technology is being adopted to meet the customers requirements. As shown in Fig. 25.7.1, an SoC that implements all of the standards and frequency bands of a mobile TV in a 65nm CMOS is presented in this paper. This RF SoC consists of three RF front ends, a dual-mode analog baseband filter supporting lowpass filtering and complex bandpass filtering, a digitally controlled programmable-gain amplifier (PGA), wideband VCO/PLL, DCXO, data converters, demodulator, forward error correction (FEC), hardwired multiprotocl encapsulation forward error correction (MPE-FEC), ARM CPU and SRAM. This mobile TV RF SoC reduces board area and complexity while cutting system design time.

A multi-standard multi-band tuner for mobile TV SoC with GSM Interoperability

A multi-standard multi-band tuner for mobile TV SoC satisfying the GSM850 & GSM900 Interoperability (IOP) is presented. The single-chip SoC satisfies all requirements of DVB-H/T, ISDB-T, and DAB application with margin. Moreover, this SoC meets not only the GSM900 IOP which is described in MBRAI 2.0, but also GSM850 IOP, in DVB-T/H mode. To suppress GSM transmitter signal in UHF band, LC-tuned load and tunable input matching scheme are adopted in UHF LNA. The SoC consists of three RF LNAs covering the 174 to 248MHz (VHF), 470 to 862MHz (UHF), and 1450 to 1490MHz (L-BAND) bands, dual mode analog baseband filter supporting low pass filtering for direct conversion in DVB-H/T mode and complex band pass filtering for low-IF conversion in ISDB-T 1-segmentation and DAB. The measured sensitivity at UHF for the QPSK 1/2 DVB-T mode is under −95.5dBm with GSM rejection filter.

CMOS DSB Transmitter With Low TX Noise for UHF RFID Reader System-on-Chip

This paper presents a new design for a CMOS double-sideband (DSB) RF transmitter (TX) integrated circuit (IC) for UHF RF indentification (RFID) reader system-on-chip. Due to the strong demand for high linearity, low TX noise, and low cost, a CMOS passive up-conversion mixer with an adaptive bias circuit is proposed. High linearity of the passive mixer can be maintained over a wide range of dc levels from the dc-coupled IF signals using the proposed adaptive biasing circuit. A linear two-stage CMOS power amplifier (PA) follows the up-conversion mixer so that the overall third-order output intercept point (OIP3) of the two-stage PA is improved by the optimized design of the first stage in its biasing condition, the cell size, and due to inter-stage matching. The designed TX IC is fabricated using a 0.18-μm standard CMOS process and the implemented passive mixer exhibits a low double-sideband noise figure (DSB NF) of 4 dB and a high OIP3 of 13.3 dBm. The implemented PA exhibits a high-output 1-dB compression point (OP1dB) of 18 dBm, and a clear sweet spot in OIP3 of as high as 36.8 dBm at the two-tone average output power of 10 dBm. The implemented overall TX IC has a size of 960 × 670 × μm2 and the overall circuit performed with a gain of 17.8 dB, a high OP1dB of 17.6 dBm, an OIP3 of 28 dBm, and has a low DSB NF of 11.2 dB while consuming a biasing current of 58 mA from a 3.3-V supply. The proposed design also satisfies the spectral mask of the RFID standard for an output power of up to 18 dBm for the double-sideband amplitude shift-keying signals.

A triband 65nm CMOS tuner for ATSC mobile DTV SoC

A triband 65nm CMOS tuner is designed and implemented for first ATSC mobile DTV SoC. It supports VHF-I, VHF-III, and UHF bands. The tuner achieves a 2.5/3.0/4.0dB NF at VHF-I, VHF-III and UHF band respectively, while consuming less than 100mW. By using narrowband LNA architecture with input and load tuning ability, it can meet linearity requirement for ATSC mobile with small power consumption. It also automatically calibrates baseband low-pass filter cut-off frequency and LNA LC load resonant frequency.

Second order nonlinearity analysis of Gilbert mixer

Second order nonlinearity of Gilbert mixer is analyzed. The harmonic generations at each part of the mixer are analyzed and are combined to predict the over-all mixer behavior. We include non-ideal tail current source and nonlinear current gain of BJT, which have been neglected in previous works but have significant effects.Second order nonlinearity of Gilbert mixer is analyzed. The harmonic generations at each part of the mixer are analyzed and are combined to predict the over-all mixer behavior. We include non-ideal tail current source and nonlinear current gain of BJT, which are neglected in previous works but have significant effects.

A Mixer With Third-Order Nonlinearity Cancellation Technique for CDMA Applications

A feedforward technique to improve the third-order nonlinearity of mixers in a direct conversion transceiver is presented. The third-order intermodulation (IM3) generated by the main transconductance (Gm ) stage of mixer with inductively degenerated emitter is cancelled by that generated by the sub-Gm stage with degeneration resistor. The circuit allows the mixer to be optimized independently, and has minimal impact on noise figure (NF), gain, area, and current consumption. The proposed technique reduced IM3 by approximately 16 dB with a current increase of approximately 7%. The mixer achieved an input-referred third-order intercept point of 5 dBm, a gain of 37 dB, and an NF of 9.8 dB drawing 7.9 mA from a 2.85-V supply. The transceiver including the calibration circuitry was implemented in a SiGe bipolar transistor with fT= 35GHz for U.S. cellular code division multiple access application

A 0.65V 1.2mW 2.4GHz/400MHz dual-mode phase modulator for mobile healthcare applications

A 0.65V 2.4GHz/400MHz digital-intensive phase modulator is implemented in 65nm CMOS. In ultra-low voltage design, the two-point modulator suffers a lot from the DCO nonlinearity. In this work, we employ a 2.4GHz semidigital fractional-N PLL with an FIR filter embedded 1-bit high-pass modulation to overcome the nonlinearity problem in the conventional two-point modulator. The 400MHz modulator performs an FIR-embedded OQPSK modulation to reduce the spectral regrowth in high frequencies. For compact area and low voltage design, an inverter based phase interpolator with a harmonic filtering technique is designed after generating multiphase signals directly from the 2.4GHz output. The 1Mb/s GFSK 2.4GHz and the 10Mb/s OQPSK 400MHz modulators consume 0.94mW and 1.2mW and achieve the EVM values of 5.7% and 6.4% respectively.

An RF receiver for multi-band inter- and intra-band carrier aggregation

An RF receiver for carrier aggregation employing a low noise amplifier with a current reusing technique and a frequency-band switchable transformer is demonstrated in a 28nm LP CMOS technology. The proposed single-ended low-noise amplifier can support multiple-channel RF signals for both inter- and intra-band carrier aggregation with high performance and low DC current consumption. Moreover, a frequency-band switchable transformer is developed to realize a size-efficient receiver for handling three carrier components carrier aggregation. The receiver operates at frequency bands, ranging from 0.7 to 2.7 GHz. The receiver has conversion gain more than 70 dB and noise figure of less than 3.5 dB for all carrier aggregation combinations.

A dual-band digital TV tuner for CMMB application SoC

A dual-band digital TV tuner for CMMB application SoC is presented. The single-chip SoC satisfies all requirements of CMMB application with margin. Moreover, the SoC meets the GSM IOP which means the co-operation GSM transmitter and mobile TV reception. To suppress GSM transmitter signal in UHF band, LC-tuned load and tunable input matching scheme are adopted in UHF LNA. The SoC consists of two RF LNAs covering the 470 to 798MHz (UHF), and 2635 to 2660MHz (S-BAND) bands, an analog baseband filter supporting low pass filtering for direct conversion, and ΔΣ fractional-N synthesizer with one VCO. The measured sensitivity at UHF for the QPSK mode is −9.8dBm with ADC clock shift scheme.