Jinman Han

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth

This paper describes a 32-bank 1 Gb DRAM achieving 1 Gbyte/s (500 Mb/s/DQ pin) data bandwidth and the access time from RAS of 31 ns at V/sub cc/=2.0 V and 25/spl deg/C. The chip employs (1) a merged multibank architecture to minimize die area; (2) an extended small swing read operation and a single I/O line driving write scheme to reduce power consumption; (3) a self-strobing I/O schemes to achieve high bandwidth with low power dissipation; and (4) a block redundancy scheme with increased flexibility. The nonstitched chip with an area of 652 mm/sup 2/ has been fabricated using 0.16 /spl mu/m four-poly, four-metal CMOS process technology.

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

A monolithic 64 Gb MLC NAND flash based on 21 nm process technology has been developed. The device consists of 4-plane arrays and provides page size of up to 32 KB. It also features a newly developed asynchronous DDR interface that can support up to the maximum bandwidth of 400 MB/s. To improve performance and reliability, on-chip randomizer, soft data readout, and incremental bit line pre-charge scheme have been developed.

A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology

The market growth of mobile applications such as smart phones and tablet computers has fueled the explosive demand of NAND Flash memories having high density and fast throughput. To meet such a demand, we present a 64Gb multilevel cell (MLC) NAND Flash memory having 533Mb/s DDR interface in sub-20nm technology. Large floating-gate (FG) coupling interference and program disturbance are major challenges to impede the scaling of NAND Flash memories in sub-20nm technology node [1]. In this paper, we present correction-before-coupling (CBC) reprogram and P3-pattern pre-pulse scheme, allowing us to overcome large FG coupling interferences. We improve program disturbance by inventing inhibit-channel-coupling-reduction (ICCR) technique. In addition, we achieve a 533Mb/s DDR interface by employing a wave-pipeline architecture [2].

A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory

We have developed a new 3-bit programming algorithm of high performance TLC(Triple-level-cell, 3-bit/cell) NAND flash memories for 20nm node and beyond. By using the proposed 3-bit algorithm based on reprogramming with SLC-to-TLC migration, performance and BER is improved by 50% and 68%, respectively, compared to conventional method. The proposed algorithm is successfully implemented in 21nm 64Gb TLC NAND flash product that provides 8MB/s write and 400MB/s read throughputs.

A 7MB/s 64Gb 3-bit/cell DDR NAND flash memory in 20nm-node technology

Recently, the demand for 3b/cell NAND flash has been increasing due to a strong market shift from 2b/cell to 3b/cell in NAND flash applications, such as USB disk drives, memory cards, MP3 players and digital still cameras that require cost-effective flash memory. To further expand the 3b/cell market, high write and read performances are essential [1]. Moreover, the device reliability requirements for these applications is a challenge due to continuing NAND scaling to sub-30nm pitches that increases cell-to-cell interference and disturbance. We present a high reliability 64Gb 3b/cell NAND flash with 7MB/s write rate and 200Mb/s asynchronous DDR interface in a 20m-node technology that helps to meet the expanding market demand and application requirement.

A 32-bank 1 Gb DRAM with 1 GB/s bandwidth

This 32-bank 1 Gb DRAM features: (1) a merged bank architecture (MBA) that results in only 3% die area penalty for 32-bank operation; (2) a source-synchronous I/O interface (SSI) that achieves 1 GB/s bandwidth with low power consumption; (3) flexible block redundancy that allows freedom of repair to anywhere within each half-Gb array; and (4) extended small swing read and single-I/O line driving write which result in 30% power reduction. The DRAM chip is implemented in a 0.16 /spl mu/m twin-well CMOS process.

Adaptive Multi-Pulse Program Scheme Based on Tunneling Speed Classification for Next Generation Multi-Bit/Cell NAND FLASH

As device technology is scaling down, Vths of NAND flash cell show a wide distribution due to process variations such as random dopant fluctuation, etc. Since the extension of Vth distribution is directly related to degradation of program performance of NAND flash, it is more challenging to meet the market requirements for applications such as solid-state drivers (SSD). This paper presents a novel program scheme, called Adaptive Multi-pulse Program (AMP), for the scaled multi-bit/cell NAND flash devices. In the proposed program scheme memory cells are classified into several groups based on their own program speeds. F-N tunneling characteristic of NAND cell array is considered in determining the level of program bias for each group. Adaptive program pulses are applied to the predefined groups so that cells reach their target verify level at the same time, regardless of the difference of their program speed. Our experimental results show that AMP achieves 20% improvement on program performance due to the reduction of the number of verify executions by 39% in 3-bit/cell architecture NAND flash memory of 21 nm CMOS technology.

Session 7 overview: Nonvolatile memory solutions

Market demand for higher density, higher performance but lower price nonvolatile memory is increasing. This year, NAND Flash memories answer such demand with more evolved 3D technologies such as 48-layer stacking and peripherals under the cell array while PCRAM introduces an MLC-enabling scheme to double its density. Emerging memories pursue a system-level contribution for higher performance and lower energy consumption by replacing the volatile memory blocks.

F2: VLSI power-management techniques: Principles and applications

Across the spectrum of microelectronics applications, power management is critical to the enabling of power-efficient products. This Forum will provide practicing circuit designers with a summary of power-management techniques, including perspectives from a wide range of product applications, and an outlook for the future in the context of coming challenges. The first four speakers in this Forum will present the general principles in development today, including power-gating and state-retention modes, PLL/DLL techniques for dynamic frequency scaling, integrated voltage regulators for dynamic voltage scaling, and low-power signaling. In the second half, four speakers representing different industry perspectives, including microprocessors, consumer electronics, microcontrollers and mobile, and DRAM, will utilize practical case studies to detail current usage of power-management techniques and speculate on future trends.

Thickness and aspect‐ratio dependence of the magnetoresistance effect in NiCo alloy films

Films of thickness 350, 500, and 1100 A rf‐magnetron‐sputtered onto Corning 7059 glass at a substrate temperature of 250 °C were patterned into aspect ratios of from 10 to 100 with a fixed width of 10 μm by the photolithographic procedure. Gold pads were formed for electrical contacts. Magnetoresistance ratio, saturation field, and in‐plane coercivity were measured. The domain patterns were studied by the Bitter method. Results show that the magnetoresistance ratio increases as film thickness increases. In a 500‐A‐thick film, the coercivity decreases from 14 to 9.8 Oe with increasing aspect ratio due to closure domain effects.