Sanroku Tsukamoto

A 10-b 50-MS/s 820-

This 10-b 50-MSamples/s SAR analog-to-digital converter (ADC) features on-chip digital calibration techniques, comparator offset cancellation, a capacitor digital-to-analog converter (CDAC) linearity calibration, and internal clock control to compensate for PVT variations. A split-CDAC reduces the exponential increase in the number of unit capacitors needed and enables the input load capacitance to be as small as the kT/C noise restriction. The prototype fabricated in 65 nm 1P7M complementary metal-oxide semiconductor with MIM capacitor achieves 56.6 dB SNDR at 50-MSamples/s, 25-MHz input frequency and consumes 820 μW from a 1.0-V supply, including the digital calibration circuits. The figure of merit was 29.7 fJ/conversion-step under the Nyquist condition. The ADC occupied an active area of 0.039 mm2 .

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A split capacitor DAC calibration method is proposed that a bridge capacitor larger than conventional design allows a tunable capacitor to compensate for mismatch. To guarantee proper calibration, a comparator with digital timing control offset cancellation is proposed. An 8-bit successive approximation ADC with 4b+4b split capacitor DAC calibration has been implemented in 65nm CMOS, achieving 0.3LSB DNL and INL with 180fF input capacitance.

W SAR ADC With On-Chip Digital Calibration

Applications of A/D converters (ADC) in digital data reading, for example hard disk drives (HDD), digital video disk, and 10BaseT, require high speed and low error rate. Short latency is also important for HDD applications that have feedback loops. Most error correction techniques detect at thermometer code zero-to-one transition to reject bubbles (sparkle errors). These techniques require many elements, making high-speed operation difficult in CMOS. This paper describes a CMOS ADC with 2-clock-cycle latency which corrects errors after thermometer code zero-to-one transition detection.

Split capacitor DAC mismatch calibration in successive approximation ADC

Rapid growth in the demand for “Green-IT” or medical applications requires power efficient ADCs. SAR ADC power scales with CMOS technology because it does not need operational amplifiers, which are getting difficult to design in deeply scaled CMOS. Recent published SAR ADCs have no static current, which improves energy efficiency [1, 2]. Split capacitor digital-to-analog converter (CDAC) is one of the best architectures for high resolution SAR ADC, but is very sensitive to the splitting capacitor because of its fractional value and parasitic. Conventional SAR ADC needs approximately 10 times faster external clock if it has no internal clock generator. However the internal SAR clock generation enables the external clock frequency to be the same as the sampling rate, but suffers from unstable operation caused by large PVT delay variation. This ADC is designed with on-chip digital calibration techniques, comparator offset calibration, CDAC linearity error calibration and internal clock frequency control to compensate for the PVT variation. The ADC is integrated in 65nm CMOS and achieved 10b at 50MS/s while consuming 820µW from a 1.0V supply.

A CMOS 6-b, 400-MSample/s ADC with error correction

A low-voltage design is developed for amplifiers in the pipelined ADC, regulating overdrive voltage to be constant over PVT variations. A prototype 10b 80MS/S pipelined ADC is fabricated in a 90nm CMOS process. The ADC consumes 6.5mW from a 0.8V supply and occupies 1.18 times 0.54mm2

A 10b 50MS/s 820µW SAR ADC with on-chip digital calibration

A 9b 100MS/s successive approximation register (SAR) ADC has been implemented in 65nm CMOS, with an active area of 0.012mm2. A tri-level based charge redistribution technique improves DAC switching energy efficiency and settling time, which is achieved by connecting bottom plates of differential capacitor arrays. The ADC achieves an SNDR of 53.1dB (8.53 ENOB) and consumes 1.46mW from a 1.2V supply, resulting in an FOM of 39fJ/conversion-step.

A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing

A 6b 3GS/s flash ADC is implemented in a 90nm CMOS process. The proposed ADC is based on an interpolating flash architecture without a T/H. To overcome the offset mismatch among comparators, an interleaved offset-calibration system is applied. Each 1-bit interpolating unit consisting of two preamplifiers and three comparators takes turns at offsetcalibration in the background. The ADC achieves the ENOB of 5.8bit at 3GS/s and the ERBW of 500MHz while consuming 90mW from a 1.2V supply. The ADC occupies a 0.28mm2 area.

A 9b 100MS/s 1.46mW SAR ADC in 65nm CMOS

In next-generation communication standards, such as OIF CEI-28G-SR and CEI-56G-VSR, the data rate has to be doubled or quadrupled compared to the current standards. Though transceivers for a data rate over 25Gb/s have been reported [1-3], designing clock-generating circuits for the receiver front-end is a significant challenge. In a phase interpolator (PI) commonly used in conventional receivers for a multi-channel configuration, both the linearity and frequency characteristics of the circuit affect the interpolation accuracy since it dynamically interpolates between reference clock signals supplied from a PLL, making the design more difficult. Blind-clock ADC-based receivers [4] eliminate the need for a clock-phase-adjusting circuit, but the area and power overheads are large due to high-sampling-rate ADCs. To address these issues, we fabricate and test a 28nm CMOS blind-clock receiver that performs phase tracking by using a data interpolator (DI). We confirm error-free operation of the receiver up to 32Gb/s with power consumption of 308.4mW from a 0.9V power supply.

A 6b 3GS/s flash ADC with background calibration

A principle of charge compensation approach for comparator offset control is analyzed. A dynamic offset control technique that employs charge compensation by timing control is proposed for comparator design in scaled CMOS technology. The analysis has been verified by fabricating a 65 nm CMOS 1.2 V 1 GHz comparator that occupies 25 times 65 mum2 and consumes 380 muW. Circuits for offset control occupies 21% of the areas and 12% of the power consumption of the whole comparator chip.

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS

A 6-bit, 1-GS/s subranging analog-to-digital converter (ADC) implemented in 65-nm CMOS is developed. The same capacitor DACs (CDACs) are used to sample the analog signals, thereby eliminating the errors between the coarse and fine decisions that occur when two different samplers are used to capture the signal. Both decisions use the same comparators, and a digitally assisted calibration circuit compensates for the errors in the different threshold levels used for the two decisions. This calibration eliminates redundant comparators, and thus, reduces the area. Reference voltages generators, which are implemented using resistor ladders in conventional subranging ADCs, are eliminated thanks to the use of the CDACs together with interpolation in the comparators. This solves two problems related to the resistor ladder, namely, the trade-off between the settling time and the static-current consumption and signal dependent on-resistance of switches connected to intermediate potential nodes. A test chip fabricated in 65-nm CMOS technology operates at 1 GS/s with SNDR of 32.8 dB. Its active area is 0.044 mm2, and its power consumption is 9.9 mW at a 1.1-V supply voltage.