Takumi Danjo

3.5 A 56Gb/s NRZ-electrical 247mW/lane serial-link transceiver in 28nm CMOS

With the rapid growth of data traffic in data centers, data rates over 50Gb/s/signal (e.g., OIF-CEI-56G-VSR) will eventually be required in wireline chip-to-module or chip-to-chip communications [1-3]. To achieve better power efficiency than that of existing 25Gb/s/signal designs, a high-speed yet energy-efficient front-end is needed in both the transmitter and receiver. A receiver front-end with baud-rate architecture [1] has been successfully operated at 56Gb/s, but additional components such as eye-monitoring comparators, phase detectors, and clock recovery circuitry as well as a power-efficient transmitter are needed to build a complete transceiver.

32Gb/s data-interpolator receiver with 2-tap DFE in 28nm CMOS

In next-generation communication standards, such as OIF CEI-28G-SR and CEI-56G-VSR, the data rate has to be doubled or quadrupled compared to the current standards. Though transceivers for a data rate over 25Gb/s have been reported [1-3], designing clock-generating circuits for the receiver front-end is a significant challenge. In a phase interpolator (PI) commonly used in conventional receivers for a multi-channel configuration, both the linearity and frequency characteristics of the circuit affect the interpolation accuracy since it dynamically interpolates between reference clock signals supplied from a PLL, making the design more difficult. Blind-clock ADC-based receivers [4] eliminate the need for a clock-phase-adjusting circuit, but the area and power overheads are large due to high-sampling-rate ADCs. To address these issues, we fabricate and test a 28nm CMOS blind-clock receiver that performs phase tracking by using a data interpolator (DI). We confirm error-free operation of the receiver up to 32Gb/s with power consumption of 308.4mW from a 0.9V power supply.

A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS

A 6-bit, 1-GS/s subranging analog-to-digital converter (ADC) implemented in 65-nm CMOS is developed. The same capacitor DACs (CDACs) are used to sample the analog signals, thereby eliminating the errors between the coarse and fine decisions that occur when two different samplers are used to capture the signal. Both decisions use the same comparators, and a digitally assisted calibration circuit compensates for the errors in the different threshold levels used for the two decisions. This calibration eliminates redundant comparators, and thus, reduces the area. Reference voltages generators, which are implemented using resistor ladders in conventional subranging ADCs, are eliminated thanks to the use of the CDACs together with interpolation in the comparators. This solves two problems related to the resistor ladder, namely, the trade-off between the settling time and the static-current consumption and signal dependent on-resistance of switches connected to intermediate potential nodes. A test chip fabricated in 65-nm CMOS technology operates at 1 GS/s with SNDR of 32.8 dB. Its active area is 0.044 mm2, and its power consumption is 9.9 mW at a 1.1-V supply voltage.

Dynamic Architecture and Frequency Scaling in 0.8–1.2 GS/s 7 b Subranging ADC

Dynamic Architecture and Frequency Scaling (DAFS) is shown to realize superlinear power scaling in high-speed analog-to-digital converters (ADCs). To achieve both high-speed operation and low power consumption, the ADC architecture is reconfigured between binary search and flash every clock cycle, relying on the conversion delay. The proposed binary search/flash architecture reconfigurable ADC can be implemented with only a small modification to conventional binary search ADCs. By live configuring, the flash operation is adaptively performed when an excess delay is detected. DAFS not only significantly improves the power scaling but also compensates for transistor speed shifts due to process, voltage and temperature (PVT) variations. Therefore, DAFS can be used to improve the design margin of high-speed ADCs. A prototype subranging ADC fabricated in 65 nm CMOS technology operates up to 1220 MS/s and achieves an SNDR of 36.2 dB with a Nyquist input frequency. DAFS is active between 820-1220 MS/s and achieves peak power reduction of 30%, when compared with the power scaling when DAFS is disabled. A peak FoM of 85 fJ/conv. was obtained at 820 MS/s, which is nearly a twofold improvement over that of previously reported subranging ADCs.

7-bit 0.8–1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

Subrange ADC with Dynamic Architecture and Frequency Scaling(DAFS) is presented, which has exponential power scaling against frequency with high-speed operation of over 1GS/s. We propose Live Configuring Technique(LCT) to adaptively configure the sub-ADC operation between binary-search and flash every clock cycle, reflecting the conversion delay. The power consumption is cut down significantly and retains high-speed operation. The prototype ADC fabricated in 65nm CMOS operates up to 1228MS/s and achieves an SNDR 36.2dB at nyquist. DAFS is active between 800-1200MS/s and when compared with the frequency power scaling with DAFS disabled, the peak power consumption cut down is 30%. Peak FoM of 85fJ/conv. was obtained at 820MS/s, which is nearly a 2x improvement compared with reported subrange ADCs.

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process

A 32-Gb/s data-interpolator receiver for electrical chip-to-chip communications is introduced. The receiver front-end samples incoming data by using a blind clock signal, which has a plesiochronous frequency-phase relation with the data. Phase alignment between the data and decision timing is achieved by interpolating the input-signal samples in the analog domain. The receiver has a continuous-time linear equalizer and a two-tap loop unrolled DFE using adjustable-threshold comparators. The receiver occupies 0.24 mm2 and consumes 308.4 mW from a 0.9-V supply when it is implemented with a 28-nm CMOS process.

A 28.3 Gb/s 7.3 pJ/bit 35 dB backplane transceiver with eye sampling phase adaptation in 28 nm CMOS

28.3 Gb/s transceiver with 35 dB channel loss equalization is presented. The transmitter deploys 3-tap feed forward equalizer (FFE). The driver employs the hybrid architecture of low voltage differential signaling (LVDS) and source-series-terminated (SST) driver which enables the low power consumption and output signal amplitude fine tune. The receiver comprised with continuous time linear equalizer (CTLE) and 2-tap loop unrolled decision feedback equalizer (DFE). It saves the power consumption by not applying DFE at the eye edge, and increases the eye margin with adaptive sampling clock phase adjustment capability. The transceiver is composed of one PLL and four lanes, occupies 1.67 mm2 and consumes 829 mW (7.3 pJ/bit).

A 6b, 1GS/s, 9.9mW interpolated subranging ADC in 65nm CMOS

A 6b 1GS/s subranging ADC with interpolating technique, which has neither a reference resistor ladder nor redundant comparators is presented. Each comparator operates twice each cycle, during coarse and fine decision, for a conversion based on digitally controlled threshold levels. The threshold levels at these decisions are different, so these are adjusted in foreground calibration. The die area is 0.04mm2 including on-chip digitally threshold control circuit, and power consumption is 9.9mW. SNDR is 32.8 dB is achieved at 1GS/s.