Santosh Sharma

Planar dual gate oxide LDMOS structures in 180nm power management technology

This paper presents a 20V-rated planar dual gate oxide NLDMOS power device structure fabricated in a 180nm power management technology. The performance of the planar dual gate device structure is compared to a conventional STI-based device and it is shown that the planar dual gate structure has superior BVds-Rsp, gm, HCI reliability, and forward safe operating area figures-of-merit. The planar dual gate structure exhibits BVds=32V/14 mΩ.mm2 specific on-resistance (and BVds=20V/7.5mΩ.mm2 for a drift length scaled version), hot carrier reliability in excess of 10 years analog lifetime in all bias regimes, and a linear forward IV characteristic. The planar dual gate architecture is scalable in rated voltage from 7V to 24V, and is an ideal component for the integration of USB switch, battery charging, backlighting, and PA envelope tracking mobile applications.

Integrated 85V rated complimentary LDMOS devices utilizing patterned field plate structures for best-in-class performance in network communication applications

This paper presents complimentary 85V-rated LDMOS devices integrated in a 180nm power management technology platform. The devices are fabricated using a design technique which utilizes tapered dielectric regions in combination with patterned floating field plated structures. The performance of the new structures are compared to conventional LDMOS structures and it shown that the floating field plated structures have superior BV_ds-R_{on, sp}, HCI reliability, and forward safe operating area figures-of-merit. These devices exhibit best-in-class BV_ds-R_{on, sp} figure-of-merit (NLDMOS : BV_ds=130V/R_{on, sp}=195mΩ.mm² and PLDMOS : BV_ds=140V/R_{on, sp}=530mΩ.mm²) and hot carrier reliability in excess of 10 years analog lifetime for rated V_DS = 85V and full range of V_GS. These devices enable cost effective integration of PoE systems with multiple interface channels and auxiliary switching regulators.

A high-resistivity SiGe BiCMOS technology for WiFi RF front-end-IC solutions

We present for the first time a novel high resistivity bulk SiGe BiCMOS technology that has been optimized for a WiFi RF front-end-IC (FEIC) integration. A nominally 1000 Ohm-cm p-type silicon substrate is utilized to integrate several SiGe HBTs for power amplifiers (PAs), a SiGe HBT low-noise amplifier (LNA), and isolated nFET RF switch device. Process elements include trench isolation for low-loss passives and reduced parasitic coupling, and a lower-resistivity region for the FETs to minimize changes to the circuit library.

Novel high voltage LDMOS using a variable fermi-potential field plate for best switching FOM and reliability tradeoff

In this paper, we discuss the fundamental design tradeoff among specific on-resistance (Ron, sp), gate charge (Cgg), quasi-saturation, and reliability characteristics for an integrated high voltage LDMOS. A novel patterned gate design is proposed and implemented in a 120V-rated NLDMOS. Optimal design characteristics are demonstrated with 30% improvement in switching FOM (Ron, sp*Qgg) and a robust Id, lin shift passing 15 years lifetime specification. The new design technique is proven to significantly improve the high voltage LDMOS design tradeoff.

A 90 to 170V scalable P-LDMOS with accompanied high voltage PJFET

A novel JFET redesign of a laterally scaled P-LDMOS device is presented. The P-LDMOS device has excellent Rsp as it is scaled from 90V to 170V operation. This P-LDMOS design is modified to produce a 100V PJFET with good turn-off characteristics and a relatively low Vpinch of 3-7V.