Max G. Levy

Hot carrier stress degradation modes in p-type high voltage LDMOS transistors

The hot carrier stress induced device degradation of a p-type LDMOS high voltage transistor is investigated at different stress conditions. The influence of shallow trench corner rounding and carbon ion implantation into the shallow trench region is discussed. Numerical device simulations, charge pumping measurements and electrical characterisations are used for these investigations.

The effect of mask substrate and mask process steps on patterned photomask flatness

Photomask substrate, blank, and finished mask flatness are becoming more serious concerns for photomask fabrication. Most commercial and captive mask houses now use a combination of mask blanks at various flatness levels from >2.0um to <0.5um, measured as total indicated range, or TIR. As mask feature sizes are reduced, depth of focus becomes significantly smaller, driving the need for tighter flatness specifications. Photomask blank suppliers generally specify mask blank flatness based on measurements of quartz substrates before films are deposited. The mask substrates start with unique, non-flat shapes resulting from polishing and are further deformed by the stress of deposited films. Mask patterning, which removes some of the deposited films, has the potential to change the shape and flatness of the mask. The attachment of a pellicle and frame also has the potential to distort the mask. Since the goal of the mask maker is to provide a finished mask meeting all requirements, including flatness, it is important to understand the effects of each step in the flatness life of the photomask. This paper provides flatness data from the following process steps: quartz substrate, chromium coating, phase shifter coating, resist coating, patterned mask and pelliclized mask. A correlation is made of substrate and blank flatness and shape to finished mask flatness, with proposed practical guidelines for control of final mask flatness.

Drift design impact on quasi-saturation & HCI for scalable N-LDMOS

In this paper, we discuss the scalable NLDMOS design in a 0.18μm HV-CMOS technology. The design impacts in quasi-saturation are compared between the 25V and 50V NLDMOS to demonstrate the implications in output and fT characteristics. The STI depth sensitivity in DC, ac and HCI characteristics is investigated. The results prove a very robust design, featuring <10% Idlin shift over 10 year lifetime for +/−10% STI depth variations.

Process for improved reflectivity uniformity in extreme-ultraviolet lithography (EUVL) masks

Fabrication of EUVL masks requires formation of both a repair buffer layer and an EUV absorber layer on top of a molybdenum/silicon (Mo/Si) multilayer coated mask blank. Alteration of the Mo/Si multilayer during etch, repair or cleaning of the EUVL mask can be detrimental to the reflectivity and thus the functionality of the final mask. IBM’s Next Generation Lithography (NGL) group has reported on EUVL mask fabrication based on an absorber of low stress chromium (Cr) and a buffer layer of silicon dioxide (SiO2). Due to poor etch selectivity between SiO2 and the underlying silicon capping layer, the finished masks had non-uniform and reduced EUV reflectivity after processing. This led to the development of an alternative absorber stack combination of an absorber layer of low stress TaNx on a buffer layer of low stress Cr. This paper describes the improved reflectivity uniformity of this type of mask along with several aspects of mask quality, such as CD control and image placement.